A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is stimulation using a 0.18μm CMOS process. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The tiny photo current received by the receiver AFE is amplified to voltage swing of 400. The results indicate that, with a photodiode parasitic capacitance of 500fF and the bonding pad parasitic capacitance of 200fF between which a 2-mm bond wire is inserted at the input node, the AFE provides a conversion gain of up to 89.21 dB and 3 dB bandwidth of 9.78 GHz. Operating under a 1.8V supply, circuit power dissipation is 95 mW and its sensitivity is 18.5μA for BER of 10-12

An inductorless circuit for limiting amplifiers is present. With the third-order interleaving active feedback, the bandwidth of this circuit could be enhanced while keeping a suppressed gain. The amplifier is simulation in a 0.18μm CMOS technology. The results show that the circuit consuming a DC power of 90mW with a 1.8V supply voltage, its voltage gain is about 42.6dB, the 3dB bandwidth of the circuit is 10.96GHz.The limiting amplifier circuit can be used in the STM-64 optical fiber communication system.