The physical unclonable function (PUF) of the ring oscillator (RO) is applied to key generation and other fields due to its excellent physical characteristics and simple implementation on FPGA. However, the traditional frequency comparison method uses the sign bit of two ROs' frequency difference which can only extract one bit of entropy, and the bit error rate (BER) of the response always exceeds 1% without error correction schemes. In this paper, we designed RO based on FPGA LUT unit in a single CLB, and proposed a method of getting difference after summing the first-order frequency difference, which we called Difference on Summed Difference (DSD) method. According to experimental measurement results, the DSD method can achieve the BER of 0.39%, and the uniqueness of 50.30%. In order to obtain more entropy, we proposed a composed entropy extraction method which combined the DSD method with the existing higher-order difference method. Experimental results demonstrated that the composed method totally obtained 32-bit response with the BER of 0.84% and the uniqueness of 49.15% while the BER of the existing higher-order difference method is 1.85%.
Abstract:A novel planar antenna with WiMAX and WLAN bandnotched characteristics is presented for ultra-wideband (UWB) applications. The UWB antenna consists of a staircase-shaped radiating element, a microstrip feedline and a modified ground plane. To realize WiMAX band-notched characteristic, a pair of hook-shaped slots is etched on the radiating element. Two folded stubs extending from the ground plane are used to reject the WLAN band for the first time. The antenna meets a bandwidth from 2.95 to 11.6 GHz, with two notchedbands of 3.25-3.95 GHz (WiMAX) and 5.00-6.50 GHz (WLAN), respectively. Measured and simulated results of the impedance bandwidth, gain, and radiation patterns are presented and discussed.
The accuracy of Convolutional Neural Networks (CNNs) has exceeded the human level in many fields, but the high computation complexity is one of the main challenges for CNNs applied in the mobile or embedded devices. In this paper, we provide a hardware accelerator scheme for the convolution operations in CNNs, which adopts the bit-serial systolic architecture. Implementation results show that the proposed scheme can reduce the area by about 64%, increase the maximum frequency by about 4.4 times and increase the hardware efficiency by about 1.2 times compared with the state-of-the-art Eyeriss architecture.
Abstract. In this paper, through the analysis of node for low turnover rate, we put forward a new method to generate test vector, and based on the node of the incentive for many times, for low turnover rate can significantly increase the Trojan detection sensitivity, in order to better the combination of side channel detection method for hardware Trojan detection. This paper puts forward several important contributions: 1) it provides detailed statistical method to generate test vector, it can generate high quality test vector, in any small Trojan instance is created in high relative activities; 2) it analyzes the effectiveness of the generated test vector in the Trojan coverage, and greatly improves the sensitivity of the side channel. The simulation results show that the test can significantly increase the sensitivity of the Trojan horse, so that the Trojan detection is more effective for the side channel analysis.
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