Phase-locked loops are used in a variety of applications, such as frequency synthesis/clock and data recovery. The nature of these applications requires high accuracy for predicting the PLL nonlinearities and dynamics during the design process, which thereby requires prohibitively expensive transistor-level simulation. In this paper we propose a compact behavioral model for voltage-controlled oscillators, which are the key components of PLLs, and the most difficult to macromodel due to their dynamic, large-scale nonlinear behavior. Unlike previous works, our approach follows a systematic modeling of nonlinear dynamics in a topology independent manner. We demonstrate that our model can reduce the system-level simulation runtime significantly without sacrificing the required accuracy. IntroductionPhase-locked loops (PLLs) have found their way in many important applications, such as frequency synthesis and clock/data recovery. The performance validation of a PLL at the system level generally requires transistor-level simulation with tight accuracy control. This accuracy requirement, however, combined with the the nonlinearities and dynamics inherent in a complex PLL, lead to prohibitively expensive simulation runtime to evaluate key performance specifications such as acquisition time, capture/lock range and phase noise. In many cases, a full SPICE simulation of the complete PLL can even become infeasible based on the meantime to failure for the computer. For this reason, compact macromodels of the key PLL components are desired to be substituted in place of the actual transistor-level models without sacrificing any of the required accuracy. A key component of the PLL (Fig. 1) is the voltage-controlled oscillator (VCO), which has dynamic large-scale nonlinear behavior that substantially impacts the overall performance of the PLL. Fig. 1. Block diagram of a PLL.Referring to the block diagram of a PLL in Fig. 1, the phase detector and loop filter can be readily modeled using behaviorallevel or circuit-level models that can capture the nonidealities, including the weak nonlinearities. However, the nature of the VCO makes it a very challenging modeling problem. The output frequency/phase of the VCO is a nonlinear function of the input control voltage (Fig. 2). Moreover, the output of the VCO is designed to be very sensitive to slight variations in the input control voltage, which makes the dynamic response of the VCO very important. Phase (frequency)-domain models of the VCO have been used in the past [1] [2][7] to speed-up the simulation, and significant progress has been made in analyzing the behavior of these oscillators, especially in terms of their phase noise [8][9][10][11][12]. The static nonlinear behavior can be captured easily by sweeping the input control voltage and measuring the output frequency [1][2], but modeling the dynamics is much more challenging [3][4][5][6]. Most attempts for modeling the dynamics are very simplistic and do not guarantee sufficient accuracy. In this paper we propose a systematic app...
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog system architectures in the early phases of design; and (2) how to hierarchically propagate performance specifications from system level to circuit level to enable independent circuit block design. Importantly, due to the inaccuracy of early-stage system-level models, and the increasing magnitude of process and environmental variations, the system-level exploration must leave sufficient design margin to ensure a successful late-stage implementation. Therefore, instead of minimizing a design objective function, and thereby converging on a constraint boundary, we apply a novel performance centering optimization. Our proposed methodology centers the analog design in the performance space, and maximizes the distance to all constraint boundaries. We demonstrate that this early-stage design margin, which is measured by the volume of the inscribed ellipsoid lying inside the performance constraints, provides an excellent quality measure for comparing different system architectures. The efficacy of our performance centering approach is shown for analog design examples, including a complete clock data recovery system design and implementation. 0-7803-9254-X/05/$20.00 ©2005 IEEE.
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