unlike graphene, the existence of bandgaps (1-2 eV) in the layered semiconductor molybdenum disulphide, combined with mobility enhancement by dielectric engineering, offers an attractive possibility of using single-layer molybdenum disulphide field-effect transistors in low-power switching devices. However, the complicated process of fabricating single-layer molybdenum disulphide with an additional high-k dielectric layer may significantly limit its compatibility with commercial fabrication. Here we show the first comprehensive investigation of processfriendly multilayer molybdenum disulphide field-effect transistors to demonstrate a compelling case for their applications in thin-film transistors. our multilayer molybdenum disulphide field-effect transistors exhibited high mobilities ( > 100 cm 2 V − 1 s − 1 ), near-ideal subthreshold swings (~70 mV per decade) and robust current saturation over a large voltage window. With simulations based on shockley's long-channel transistor model and calculations of scattering mechanisms, these results provide potentially important implications in the fabrication of highresolution large-area displays and further scientific investigation of various physical properties expected in other layered semiconductors.

High contact resistance is one of the primary concerns for electronic device applications of two-dimensional (2D) layered semiconductors. Here, we explore the enhanced carrier transport through metal-semiconductor interfaces in WS2 field effect transistors (FETs) by introducing a typical transition metal, Cu, with two different doping strategies: (i) a "generalized" Cu doping by using randomly distributed Cu atoms along the channel and (ii) a "localized" Cu doping by adapting an ultrathin Cu layer at the metal-semiconductor interface. Compared to the pristine WS2 FETs, both the generalized Cu atomic dopant and localized Cu contact decoration can provide a Schottky-to-Ohmic contact transition owing to the reduced contact resistances by 1 -3 orders of magnitude, and consequently elevate electron mobilities by 5 -7 times higher. Our work demonstrates that the introduction of transition metal can be an efficient and reliable technique to enhance the carrier transport and device performance in 2D TMD FETs. IntroductionTungsten disulfide (WS2) with a semiconducting 2H phase is one of two-dimensional (2D) transition metal dichalcogenides (TMDs) exhibiting a series of unique properties, such as strong spin-orbit coupling, band splitting, and high nonlinear susceptibility 1-3 . Especially for future nanoelectronic applications, WS2 stands out as a promising channel material compared to other 2D semiconductors. For example, WS2 has a direct bandgap of 1.4 -2.0 eV 4-7 for the monolayer and an indirect bandgap of 1.2 -1.3 eV 4-6 for the bulk crystals. The carrier mobility of WS2 has been theoretically predicated up to ~5,300 cm 2 /Vs at 77 K 8 and ~700 -1,100 cm 2 /Vs at room temperature 8,9 , which exceeds most of the commonly used semiconducting TMDs such as MoS2 (340 cm 2 /Vs), MoSe2 (240 cm 2 /Vs), WSe2 (705 cm 2 /Vs), owing to the relatively small effective mass (0.34m0 for electrons and 0.46m0 for holes, where m0 is the free electron mass) 7 . Although the experimentally demonstrated electron mobilities, limited by Coulomb impurities, charge traps, surface defects and roughness, are much lower than the theoretical predication, new techniques have been developed to practically improve the mobility, for example, by exploiting h-BN 10 or high-k 11 dielectrics. For the application of field-effect transistors (FETs), monolayer WS2 FETs are predicated to outperform other TMD FETs in terms of the on-state current density (JD,on) for both p-and n-type transistors (~2,800 μA/μm for the monolayer WS2 versus 2,200 -2,400 μA/μm for the monolayer MoS2, MoSe2, and MoTe2 FETs) 11 . In addition to the carrier mobility, the pristine hysteresis width of WS2 during reliability tests is the lowest compared to MoS2, MoSe2and MoTe2 FETs 12 . The current on/off ratio at room temperature has been experimentally demonstrated up to ~10 6 for the monolayer WS2 FETs 13,14 and to ~10 8 for the multilayer WS2 FETs 15 . A nearly ideal subthreshold swing (SS) of 70 mV/decade at room temperature has been demonstrated in a simple back-gated WS2 FET th...

Tunnel field-effect transistors (TFETs) are under intense investigation for low-power applications because of their potential for extremely low subthreshold swing (SS) and low off-state leakage [1]. III-V semiconductors with small effective mass and near broken band alignment are considered to be ideal for TFETs in that they promise high on-current and ION11oFF ratios [2][3]. In this paper, we report the first demonstration of an InAs/Alo.45Gao.55Sbheterojunction TFETs fabricated using an optical-lithography-only, self-aligned process and also investigate the effects limiting the InAsl Alo.45Gao.55Sb TFET performance. Fig. I(a) shows a cross section of the n-channel InAs/Alo.45Gao.55Sb TFET in a new tunneling geometry with the tunnel transport directed normal to the gate .. The TFETs were grown by molecular beam epitaxy (MBE) on a GaSb substrate. The epitaxial structure, starting from the substrate, consists of: 200 nmAISbl AlAs superlattice buffer layer, 300 nm of n+InAso9ISbo09,1O nm of n-InAs (Si-doped, 1 x 10 17 cm-\ 110 nm of p+GaSb, and 30 nm of p+AlxGal_xSb (Be-doped, 4 x 10 18 cm-3 ), with the Al composition x increased in three steps from 0 to 0.45, and concluding with a top 30 nm n-InAs layer (Si-doped, 1 x 10 17 cm-\ Three samples were processed; for one sample TFETs were fabricated on the heterostructures as grown, while in the other two the top InAs layer was thinned using Citric acid:H202 (1: 1) to 22 nm and 15 nm thickness, respectively. A 7 nm thick Ab03 gate dielectric was deposited by atomic layer deposition (ALD) immediately after cleaning in IHCI:IH20 for 30 s. A Ti/W/SiNx gate stack was blanket-deposited, then patterned using optical lithography, and reactive-ion etched (RIE). Plasma-enhanced chemical vapor deposition (PECVD) SiNx sidewalls were then formed around the gate, followed by removal of Ab03 gate dielectric using AZ 400K developer. After drain metallization and lift-off (Ti/Au), InAs was selectively etched in Icitric acid:IH202, followed by a selective AIGaSb etch using tartaric acid:H202:HCI:H20 (3.75 g : 4 ml : 40 ml : 400 ml) until the AIGaSb under the drain and the SiNx spacer was removed, forming the undercut mesa structure. Fig. I(b) shows the cross sectional image of a fabricated InAs/AIGaSb vertical TFET, taken after cross sectioning in a focused-ion beam and imaging by scanning electron microscopy (FIB/SEM). The SEM images clearly indicate that the InAsl AIGaSb tunnel junctions were fully overlapped by the gate electrode. Shown in Fig. 2 (a), (b) and (c) are the measured ID -VDS characteristics of a TFET with a 30 nm, 22 nm and 15 nm top InAs thickness at 300 K, respectively. The on-current is about 1200, 275 and 1 J.lA/�m at VDr 0.5 V, respectively, while the gate leakage is smaller than the drain current. The low on-current of the 15 nm InAs TFET is due to the overetching of the AIGaSb under the gate and consequent higher access resistance. Shown in Fig. 3(a) and (b) are the ID -VGS characteristics of TFETs with 22 nm and 15 nm of InAs at 300 K, respectively. While the dr...

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