A FAMILY of 8-bit ECL microprocessor bit slices with 1000-gate complexity for use in main frames, minicomputers and special purpose machines will be described. The devices are built in Isoplanar' subnanosecond ECL technology M4th full temperature compensation3'4'5'6.Future high performance data processing systems require faster processing rates, higher machine densities, and greater system reliability. These requirements can only be met by use of hgher speed integrated circuits with more on chip integration and optimum packaging techniques. A standard subnanosecond ECL MSI family having internal gate delays of less than 600ps has partially satisfied these requircments. However, interconnect and package delays represent the largest percentage of the logic stage delay in system applications at these speeds; therefore, LSI is required to improve ac performance. A family of 8-bit processor slices is being developed to expand and complement the earlier family. Each slice is supplied in a JEDEC 68 pin leadless package for use in an air-cooled environment.The family includes an Address and Data Interface Unit (ADIU), a byte-wide cascadable building block, designed to handle bus-to-bus data and address transfers, manipulation, and temporary storage. It contains three 9-bit (8-bit plus parity) bidirectional data buses for communication with a variety of system data paths and register files; Figure 1. Parity is checked and generated for information entering and exiting the ADIU, respectively. One of 27 instructions is decoded and executed during the active state of the clock (CLK). The instruction set includes a wide range of logic operations, single bit left/right shifts, binary 2's complement addition and subtraction, decimal packed and unpacked arithmetic, ECC encode and correction. The two sources of the ALU can come from any of the three __ nosecond Emitter-Coupled Logic Gate Circuit Using Isoplanar 'Dhaka,
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