We discuss the implementation of a strategy designed to provide laser-lightemitting reliability assurance for 1.3-μνα InGaAsP/lnP lasers of the planar mesa, buried heterostructure type for use in a submarine cable application. The testing regimes include initial characterization (cosmetic and light-current curve inspection), passive aging (elevated temperatures [85 to 175°C] without bias, with and without humidity [<85-percent relative humidity]), overstress active aging (high temperatures [150°C], high currents [250 mAdc]), and longterm rate-monitoring active aging (elevated temperature [60°C] burn-in [3 mW/facet]). Overstress testing is designed to compel a timely (~10 2 -hour) identification of premature failures, due to modes of degradation other than the long-term ultimately controlling wear-out mode, and to stabilize transient modes. To identify premature failures of the wear-out type, survivors of overstressing are subjected to rate monitoring in which wear-out degradation rates, established in a reasonable time (~10 3 hours), may be sorted. The principal results of the important overstress aging were the detection of an initially occurring saturable degradation mode, present to some extent in most lasers, and a regimen to force its rapid stabilization, so that it would not obscure determination of the activation energy of the wear-out mode. With a credibly determined value for the latter, it was deterministically inferred from * Authors are employees of AT&T Bell Laboratories.

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When a suitable interfacial dopant, such as W, is introduced at the interface between the dielectrics of a DDC cell, the write-erase character istics of the cell are greatly improved. The useful range of the dopant con centration is determined to lie between about W u to 10 1S atoms/cm*. The interfacial dopant allows the fabrication of a DDC cell with relatively thick SiOï layers (>5θΑ). The result is a substantially permanent memory cell that can still be subjected to electrical write-erase at reasonable gatevoltage conditions.

By means of novel differential techniques, we have studied the writing and erasing dynamics of DDC cells and, in the process, uncovered a number of unexpected phenomena which play an important role in these processes. For example, we find writing currents qualitatively similar to, but considerably in excess of, those predicted earlier by Fowler-Nordheim studies on similar MOS structures. We find that these devices can be written with high and undiminished efficiency to 7–10 V of flatband shift depending on insulator thickness, and we determine the limiting source of efficiency degradation beyond these levels. In erase, we find an interesting enhancement due, we believe, to electron-electron repulsion of the net stored charge. By studying the reversible motion of the stored-charge centroid at high temperatures, we determine that the effect of the interfacial dopant on the outer insulator extends about 80 Å into this layer. Other studies indicate an effect on the thin oxide to be less than 20 Å. Low-field long-time charging results point to a Fowler-Nordheim–like writing current versus oxide field extending at least from 4.2 to 10 MV/cm, a range of no less than 109 in current density for oxide thicknesses of 80 Å or more. All these features and others were found and investigated using quite standard flatband measurements, albeit, by the use of novel patterns of writing and erasing.

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