THE CIRCUIT and process considerations for a high-speed, high-density, 16K bit, 5-V, static VMOS ROM will be presented.Present 5-V, N-channel MOS ROMs have die sizes ranging from (155 mil2 t o 170 mil2), and worst-case address access times ranging from 55011s to over 1p.s. The VMOS ROM to be discussed has a (130 mil)2 die size for 6p design rules, and a worst-case access time of 200 ns. Features which may be programmed by the user along with the data and chip enable address include a power-down option and a choice of a 2K x 8 or 4K x 4 configuration.The VMOST"' is a vertical N-channel MOS transistor whose gate is formed on the <111> face of a V-groove. A scanning electron photomicrograph and cross-section of a VMOST are shown in Figure 1. An N+ substrate is the common source of all VMOSTs. A micron or submicron P-layer determines the effective VMOST channel length in its saturation region3. A lightly doped P-type 71 layer lowers the drain-substrate capacitance and increases the drain-substrate breakdown voltage to about 25-V. The VMOST functions as a high-density, high performance switch for two reasons: (I)-it has a short (%1p) channel length controlled by diffusion and not photolithography, (2)-it is geometrically efficient; the device shown in Figure 1 has a 25p channel width, even though the surface V-groove (gate) area is only 1 o p x lop.A seven-mask (through metal) VMOS process which features double selective oxidation is used to fabricate the ROM. This mask count is one more than that of a depletion-load MOS process. The extra mask is used for the V-grooves, while various surface MOS structures are defined in a conventional manner by the other six masks. The major circuit elements created by the VMOS proccss are the VMOST, a planar enhancement N-channel MOS transistor, and an ion-implanted load resistor.Resistors are chosen as load elements over depletion loads because they have lower temperature dependence, and therefore give better worst-case power-speed values.A die picture of the ROM is given in Figure 2. The die size is 120x140 mil2. Conservative design rules were chosen to avoid photolithographic complications. Six micron lines and spaces are used throughout, except for the metal which __ MOS (VMOS) Logic." ISSCC Digest of Technical Papers, THAM 'Rodgers. T. of Double Diffused MOS Transistors," IEEE J. Solid-State Circuits, Vol. SC-10. No. 5, p. 322-331; Oct., 1975.has 7p spaces. The address-to-output access time for a typical part is shown in Figure 3. The delay through a path in which both the word line and bit line are 1OOyo programmed with V-grooves is approximately 180 ns for VDD = 5.0 V and TA = 25OC. The ROM core cell is shown in Figure 4. It is 17p x 17p or 0.45 mil2, a compromise between minimum area and fast access time. The core for minimum geometry (350 ns) VMOS ROM would be 1 4 p x 16p or 0.35 mil2 for 6p design rules. The tri-state output drivers are shown in Figure 5. The VMOS pull down device has an area of 100 mils', and can sink 9.6 mA at 0.4 V, providing a six TTL unit load capa...
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.