Future applications will require higher 1/0 counts, more lensification, lower cost and greater performance.This paper demonstrates why area-array based chip-to-substrate and substrate-to-card in terconncc ti ons are strategic, particularly solder builp flip chips (SBFC or C-4) and solder grid arrays (SGA) respectively.That is, SBFC are capable of high pin counts coupled with high yields, performance and reliability. Moreover, recently introduced SGA interconnections, both ball and column, provide substantial benefits over standard pin grid array (PGA) packages. A l s o , SGA packages possess the highest density achievable at the card level when utilized in conjunction with SBPC-Inounted die.
Future applications will require higher YO counts, more densification, lower cost, and greater performance. This paper demonstrates why area-array based chip-to-substrate and substrate-to-card interconnections are strategic, particularly solder bump flip chips (SBFC or C-4) and ceramic ball or column grid arrays (CBGAICCGA), respectively. That is, SBFC are capable of high pin counts coupled with high yields, performance, and reliability. Moreover, recently introduced CBGAICCGA interconnections provide substantial benefits over standard pin grid array (PGA) packages. Also, CBGAICCGA packages possess the highest density achievable at the card level when u t i l i in conjunction with SBFC-mounted die.
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