IntroductionDouble-gate MOSFETs are attractive because they can be scaled to the shortest gate length for a given gate oxide thickness [l]. Recent studies suggest that double gate devices can meet performance requirements down to l o r n gate length [2]. The FinFET was introduced in [3] and is a promising double-gate structure. In [4], a simplified, quasi-planar version of the FinFET exhibiting excellent performance was presented.Short channel effects can be suppressed in the FinFET provided that the gate length is at least 1.4 times the f i n thickness [4,5]. The source/drain (SID) thin fin extension regions are highly resistive so it is essential to minimize the length of the S/D thin fin extensions. In this work, we combine the simplicity of the new FinFET proce'ss flow with a selective Ge growth technique to present the first raised S/D quasi-planar FinFET devices. Device FabricationThe quasi-planar FinFET device is illustrated in Figures 1 & 2. SO1 wafers are thermally oxidized to provide 5 0 m silicon films with a 5Onm hard mask oxide. E-beam lithography is used to form silicon fins as narrow as 35nm and then the gate stack is formed, comprised of a 5Onm oxide hard mask on top of 240nm in-situ boron-doped poly-Sio,sGeo on 1.8nm SiOz gate oxide. A top-view SE.M image of a multifin device just after gate patterning is shown in Figure 3.After a double-layer spacer of 3 7 . 5~1 nitride on l o r n oxide is formed. arsenic and phosphorus are implanted to form the self-aligned S/D. A I5 hour 600°C anneal is used to recrystallize any portion of the silicon f i n amorphized by the heavy As implant. This is followed by a short 900°C activation anneal and a 45OOC forming gas anneal.After completely removing the oxide over the S/D regions, 70nm of Ge is selectively grown by LPCVD to provide the desired raised S/D. A TEM image of Ge selectively grown on a Si test wafer is shom in Figure 4. A similar technique has been used for ultra-thin body SO1 MOSFETs [63. A top-view SEN image of a FinFET (with poor alignment) after selective Ge growth is shown in Figure 5 . Ge growth can clearly be seen. The Ge thickness was limited to 701x11 to avoid bridging between the gate and the S/D. The Ge growth is followed by a phosphorus implant, 750°C activation anneal, and a 300°C forming gas anneal. No silicide or metal was used in the devices reported here. Results Measured I-V characteristics for a 90nmFinFET w i t h 7 0 m fin width are shown in Figure 6. An Idsat improvement of up to 28% results from the raised SID processing. The absence of excessive gate current indicates that bridging between the gate and S/D did not occur.Because the gate is not self-aligned to the wide S/D regions in the quasi-planar FinFET, S/D resistance can be asymmetric, particularly noticeable when the original fin width is small. The I-V characteristics shown in Fisure 7 are €or a raised SKI quasi-planar FinFET with alignment similar to the device shown in Figure 5. Reversing the source and drain changes Idsat by only 3%. Thus, even with poor ali,onment, t...
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