Abstract. This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high.
A novel inter-neuron communications method for increased scalability of Spiking Neural Networks (SNNs) is presented. Capacitive coupling is used as the communication medium with spike functions replaced by oscillatory bursts. The dependency of the coupling signals between neuron layers as a function of neuron density, frequency and track loading is predicted. High Q decoding filters and accurate frequency matching between transmitting neurons and receiving synapses was achieved using band pass filters. Micro-Electro-Mechanical Systems (MEMS) were used in the filter circuits and burst oscillators because of their high Q values. The method of fabricating the on-chip coupling capacitors and associated oscillator/filter circuits is discussed.
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