This work presents the hardware implementation of four hardware profile stream ciphers from the eSTREAM project. The hardware architectures are implemented using structural VHDL and, taking into account the simulation results, the best algorithm for hardware implementation is Trivium, with an 80-bit security level. This implementation requires 8 ALUTs, 289 registers, has a maximum frequency of 915.75 MHz and a throughput of 915 Mbps. The second is Grain-128, followed by Mickey-128 and Decim-128, which have a 128-bit security level. The designs were synthesized on the Altera FPGA Stratix III EP3SE50F484C2.
This paper presents the design of a systolic processor for DNA local pairwise alignment. The main building block of the processor is a 1D array of processing elements that allows pipeline processing to reduce the execution time with respect to software tools. We aligned two sequences of 4096 nucleotides from the ABO blood group gene of human and house mouse using ModelSim-Altera to verify the hardware design. The hardware simulation results were compared with software simulation results, showing the functionality of the design. The design can only be synthesized on the targeted FPGA for processing 256 nucleotides simultaneously due to hardware limitations (ALUTs and registers), but could be implemented for aligning larger sequences by using a bigger device or FPGA arrays. The design could also be used to implement other dynamic programming algorithms by modifying the processing element.
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