Studies have shown that driver drowsiness is one of the main causes of road accidents. It is estimated that 30% of road accidents are caused by driver drowsiness, which creates a need for driver drowsiness detection in modern vehicle systems. Previous works have shown the viability of using heart rate variability (HRV) for detecting the onset of driver drowsiness. HRV is obtained for electrocardiogram (ECG) signals, of which the power bands can be analysed to determine the physiological state of a person. This paper introduces a new method to detect driver drowsiness by classifying the power spectrum of a person's HRV data using Block-based Neural Networks (BbNN), which is evolved using Genetic Algorithm (GA). For most cases, regular Artificial Neural Networks (ANN) are not suitable for high speed and efficient hardware implementation. BbNNs are better candidates due to its regular block based structure, has relatively fast computational speeds, lower resource consumption, and equal classifying strength in comparison to other ANNs. Preliminary work has shown promising results with up to 99.99% classification accuracy using the proposed BbNN detection system for HRV data.Index Terms-Block-based neural networks (BbNNs); genetic algorithm (GA); heart rate variability (HRV); electrocardiogram (ECG); driver drowsiness;
The Transport Layer Security (TLS) protocol is currently the predominant method of implementing Internet security. This paper proposes an FPGA-based embedded system integrating hardware that accelerates the cryptographic algorithms used in the SSL/TLS protocol. OpenSSL, an open source implementation of the SLL v3 and TLS v1 protocol, is deployed in the proposed embedded system powered with a Nios-2 embedded soft-core processor. Nios2-Linux RTOS is applied, which serves to provide Ethernet connectivity, multitasking, and support for the OpenSSL library. Key cipher functions used in SSL-driven connections, which include AES-256 symmetric encryption, SHA-2 hashing, RSA-2048 publickey cryptography, are accelerated in hardware. The embedded cryptosystem is prototyped completely on an Altera Stratix II FPGA development board. Experimental results show significant improvements in performance of the SSL transactions when the proposed embedded cryptosystem is deployed in the networking system.
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