Abstract. The design challenges of voltage reference generators in CMOS technology have increased over the years in low-voltage low-power CMOS integrated circuits, constituting analog, digital, and mixed-signal modules. The emergence of hand-held power autonomous devices pushes the power consumption limit to nW regime. Along with these confrontations, limited full-scale range of data converters at low supply levels demands accurate reference voltage generators. This paper reviews the allied design challenges and discusses the evolved methodologies to tackle them. This paper also prominently surveys the sub-1 V voltage reference topologies presented in the literature along with classic bandgap based voltage reference topologies. Non-bandgap (only CMOS) based reference architectures are proven to be area-and power-e cient, but always have to be accompanied with auxiliary on/o chip trimming mechanism for high accuracy. We also provide insightful analysis of the voltage reference topologies required by the designers.
A CMOS voltage reference, which is based on the weighted compensation of thermal voltage and threshold voltage temperature variations is presented. Subthreshold NMOS transistors and resistive divider configuration are used to achieve reference voltage with low temperature coefficient. Taguchi orthogonal array technique is presented to optimize the circuit to attain precise reference voltage with high PSRR. The proposed voltage reference circuit is analyzed theoretically and compared with other methods. The circuit is designed and simulated in standard 180nm mixed mode CMOS technology. The minimum supply voltage is 1.2 V. A temperature coefficient of 3.6 ppm/ • C is achieved with line sensitivity of 0.01%/V. Moreover, PSRR at 100 Hz and 1 MHZ is -100.8 dB and -31.2 dB respectively.
A CMOS process-insensitive voltage reference gen erator, which is based on the weighted sum of thermal voltage and difference of threshold voltages, is presented. The voltage reference circuit uses high VTH and regular VTH transistors and produces reference level of 422m V. The proposed technique is analyzed theoretically and its results are compared with other methods. The circuit is designed and simulated in standard 180nm mixed mode CMOS technology for low-cost low-power applications. The circuit operates at minimum supply voltage of
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