With rapid scaling of CMOS technology, subthreshold and gate leakage mechanisms have become dominant. With feature size scaling beyond 50nm, gate leakage has become comparable to subthreshold leakage. In such a scenario, gate leakage currents can no longer be ignored in NMOS devices that are switched OFF. Previous studies on gate leakage current do not consider the effect of this component. In this paper, we study the interdependence between subthreshold and gate current by including gate current in OFF transistors and estimate minimum leakage input vectors. Performing analysis on fundamental CMOS combinational and sequential blocks has shown that the gate leakage current in OFF transistors has a significant impact on the total leakage current to the extent that the minimum leakage vectors are no longer the same when this particular leakage component is considered. Based on the factors affecting subthreshold and gate leakage currents and their interdependence, different scenarios are identified which are used in minimum leakage vector pattern estimation. In the case of stacks with variable number of transistors, a standard approach is developed in determining minimum leakage vectors.
In this paper we report on alternate solutions to protect against process variability -while also focusing on minimizing simulation time. We have investigated a variety of techniques, including the use of aerial image parameters to flag sites that might be sensitive to changes in dose, a mask error enhancement factor (MEEF) check based on biasing of the optical proximity correction (OPC) layer to reflect mask variations, and a sorting approach where sites with suspect parameters (e.g. high MEEF or poor aerial image quality, such as low slope) are simulated using multiple process conditions. All of these techniques represent shortcuts as compared to simulations of the full chip at multiple process conditions, and thus savings in CPU time. However, use of these short cuts can have several down-sides: first, increased risk of missing a real error, and second, increases in the number of false errors reported (where false errors are sites which are predicted to fail, but actually have an adequate window to allow for process variability). The challenge is to find methods to make the short cuts as selective as possible, so that they will flag all potentially failing sites, without flagging too many false errors.
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