After the occurrence of a DC-side feeder faults on HVDC transmission systems, protection and fault detection systems are anticipated to minimize their onerous effects, by initiating fault-clearing actions such as selective tripping of circuit breakers. Following the successful fault clearance, a subsequent action of significant importance, is the meticulous estimation of its location as a means to accelerate the line restoration, reduce down-time, limit recovery and repair costs, and hence elevate the overall availability and reliability of the transmission system. In order to capture DC-side fault transients for protection and fault location applications, measuring equipment is required to be placed on HVDC installations. This paper focuses primarily on reviewing the available technologies from the perspective of enabling protection, fault location and automation applications in HVDC systems. The review constitutes a mapping of protection and fault location functions, against the available voltage and current measuring technologies, ultimately unlocking insights for selecting measuring equipment based on the desirable characteristics of protection and fault location systems. The review also revealed that the frequency characteristics of each sensing scheme, primarily refers to the bandwidth of the primary sensor, whereas the overall bandwidth of the complete measuring scheme may be further restricted by the secondary converter and corresponding data acquisition system and signal processing electronics. It was also identified that the use of RC voltage dividers has prevailed for voltage measurements for HVDC applications, due to their superior advantages. The choice of a suitable device for current measurement, depends mainly on the fault detection method used and the frequency range it operates. In particular, the review revealed that fault detection and protection methods are mainly concentrated in a frequency spectrum ranging from a few kHz to 100 kHz, while fault location methods require measurements with a frequency range from 100 kHz up to 2 MHz.

This paper reviews the state of the art of DC fault discrimination and detection methods of HVDC grids, and summarises the underlying principles and the characteristics of each method. To minimize HVDC grid disturbance and power transfer interruption due to DC faults, it is critically important to have protection schemes that can detect, discriminate and isolate DC faults at high speeds with full selectivity. On this basis, this paper lists the advantages and disadvantages of the most promising fault detection methods, with the aim of articulating the future directions of HVDC protection systems. From the qualitative comparison of relative merits, the initial recommendations on HVDC grid protection are presented. Moreover, a comprehensive quantitative assessments of different fault detection methods discussed above are carried out on a generic 4-terminal meshed HVDC grid, which is modelled in PSCAD environment. The presented simulation results identify that the voltage derivative and wavelet transform are the most promising methods for DC fault detection and discrimination.

Speed and selectivity of DC fault protection are critical for High-Voltage DC (HVDC) grids and present significant technical and economic challenges. Therefore, this paper proposes a non-unit protection solution that detects and discriminates DC faults based on frequency domain analysis of the transient period of DC faults. The representation of a generic HVDC grid section and the corresponding DC-side fault signatures in the frequency domain form the basis of a generalized approach for analytically designing a protection scheme based on Wavelet Transform (WT). The proposed solution is adaptive within its design stage and offers general applicability and immunity to system changes, while the protection settings are configured for optimized performance. The scheme is validated through offline simulations in PSCAD/EMTDC and the technical feasibility of the algorithm in the real world is demonstrated through the use of real-time digital simulation (using RTDS) and Hardware-inthe-Loop (HIL) testing. Both offline and real-time simulations demonstrate that the scheme is able to detect and discriminate between internal and external faults at a significantly high speed, while remaining sensitive to high impedance faults and robust to external disturbances and outside noise.

Successful deployment of High-Voltage Direct Current (HVDC) grids necessitates effective DC fault handling strategies, which can minimize the severe consequences caused by DC faults on the AC and DC side of the HVDC grids. Therefore, this paper investigates the enhanced DC fault performance of the Customized Hybrid Modular Multilevel Converter (CH-MMC), in which a limited number of full-bridge sub-modules (FB-SMs) is added into the arms of the conventional MMC in an effort to significantly extend the timespan between fault inception and fault clearance, thus allowing the use of relatively slow and cheaper DC circuit breakers. Based on this converter, a dedicated DC fault handling strategy for CH-MMC based HVDC grids is proposed, which aims to improve the fault resiliency and security of HVDC grids for pole-to-pole faults. Moreover, the proposed DC fault management strategy guarantees the continuous operation of the grid during pole-to-ground DC faults, including full reactive power provision from the converter stations. The performance of the strategy is demonstrated using comprehensive electromagnetic transient (EMT) simulation studies conducted on an illustrative four-terminal meshed HVDC grid, which consider a range of scenarios with different fault current limiting inductors and DC circuit breaker operation times.

Low Voltage Direct Current (LVDC) distribution systems have recently been considered as an alternative approach to electrical system infrastructure as they provide the additional flexibility and controllability required to facilitate the integration of more low carbon technologies (LCTs). However, DC protection systems and, more specifically high accuracy DC fault location, have been recognised as a key challenge to facilitating post-fault network maintenance. Most of the existing fault location techniques rely on current derivative or communications-based methods that are either very sensitive to noise or require a high level of data synchronisation. Fault energy has been recognized as a reliable indicator of more accurate fault location estimations. Therefore, this paper develops a mathematical model for describing fault energy during the transient period of DC faults. The method subsequently proposes a new fault let-through energy based DC fault location working strategy to facilitate post-fault network maintenance. The proposed method does not require data synchronisation regardless of the voltage, current, and the size of the converters connected to the LVDC feeder. The capabilities of the proposed fault location strategy are validated against different faults applied on an LVDC test network in PSCAD/EMTDC and shown to be more reliable and accurate than existing methods.

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In the new era of increasingly electric aircraft, the need for reliable and safe electrical systems is more important than ever. In addition, the wide scale adoption of DC distribution is considered a key enabling technology for more efficient aircraft operation. In this context, arc fault detection devices have become a topic of interest for the aviation industry with ongoing research to characterize the impact and adequately protect against severe DC series arc faults. Although DC arc faults have been widely investigated for utility applications (such as solar photo-voltaic systems), direct adoption of current practices for validating arc detection devices is not straightforward due to the distinct aircraft operating environment. This paper provides a first of its kind, landscaping exercise of published series arc fault testing based on factors associated with aircraft applications which have the potential to influence the arc characteristics. In addition, an appraisal and associated gap analysis of published arc test platforms is undertaken in order to assess their suitability to support in-depth testing of the impact and mitigation of series arcs within future aircraft DC electrical systems and identify future testing needs in particular to better facilitate a comprehensive performance validation of new arc fault detection devices.