In this paper Radiation Hardened by Design (RHBD) Technique is used to design a high speed Phase Frequency Detector (PFD). The PFD output is not related to input duty cycle. The PFD is tolerant to Single Event Transient (SET) effect. The design is implemented using TSMC 0.35µm CMOS process. It is used in harsh radiation environments suitable for high speed space applications.
Frequency Synthesizer forms the heart of electronic communication system. Phase Locked Loop (PLL) based Frequency Synthesizers over the years has become the ubiquitous solution for generation of stable clock source. But it is a challenging task to design and develop PLL to be used in radiation environment such as in satellites, space systems and military electronics. Since impact of radiation strike on PLL is said to introduce transient faults resulting in increased timing jitter, distortion in phase, and bit flips. One or more of the above said effects can initiate false triggering which may result in incorrect data to be latched, loss of synchronization in data processing and networking. This may lead to catastrophic effect. Hence, as the stability of frequency synthesizer is of vital importance, there is a stressful need for design of radiation hard, fault tolerant frequency synthesizer. With this motivation, in this paper, a radiation hard CMOS Charge Pump PLL is designed to synthesize a 2.4GHz frequency source using 20MHz reference input frequency. The proposed radiation hard PLL design uses a hybrid Radiation Hardening By Design (RHBD) fault tolerant technique combined with redundancy, hence offering a twofold level of fortification from radiation spikes. Cadence tool was used for simulation. The PLL designed has exhibited satisfactory performance. The RHBD Charge Pump PLL in presence of radiation strike resulted in rms jitter of 128.9ps, phase noise of -94.03dbc/Hz and settling time of 159ns against the IEEE 802.11b/g standard requirement of 250ps jitter, -110dbc/Hz phase noise and 10us setting time.
The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges. Thus strengthening low cost CMOS digital design with Radiation Hardened by Design (RHBD) approach can be of paramount significance compared against the high cost Radiation Hard by Process (RHBP) approach. With this motivation, in this paper a novel and robust All-Digital-Phase Locked Loop (ADPLL) design has been developed for frequency synthesis. Our ADPLL design model encompasses multiple novelties and contributions including Feedback-Divider-Less-Counter (FDLC) based ADPLL, predictive phase-frequency detection (PFD), enhanced Time to Digital Converter (TDC) to detect next-edge occurrence of the reference clock that reduces locking period and complexity. The predictive PFD applies a phase-prediction scheme that delays the clock-edges of the reference frequency with a calibrated amount that it always aligned towards the expected frequency clock edge. It makes TDC to be narrow enough to cover the reference and oscillator jitter. Our proposed ADPLL design applied a narrow range converter (TDC) that assist phase-error prediction, correction and phase detection. The reference clock delay facilitates accurate timing relationship estimation with the variable frequency and hence performs retuning of the variable clock to reduce locking period and reduce noise. The ADPLL design has exhibited satisfactory performance for the frequency synthesis with reference frequency of 20MHz and the synthesis frequency of 2.4 GHz meeting radiation hardened features. The simulation results has revealed that the proposed Rad Hard ADPLL design can be a potential solution for space communication systems by maintaining low jitter of 340ps and power consumption of 371.7mW, as the narrow range TDC designed can detect sample radiation induced impulse noise of 20ns, 1mV and correct it.
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