This paper presents an improved low power design of a 4-bit Johnson Counter which is designed using and Clock enable method. The proposed design shows a power reduction of 5mW as compared to the conventional Johnson counter which is 7mW. Pulse triggered flip flop employed in the proposed design can save power up to 28.57% as compared to the conventional design. All the simulations were carried out using Xilinx software in SIM module.
In this paper we have presented clock gating process for low power VLSI (very large scale integration) circuit design. Clock gating is one of the most quite often used systems in RTL to shrink dynamic power consumption without affecting the performance of the design. One process involves inserting gating requisites in the RTL, which the synthesis tool translates to clock gating cells in the clock-path of a register bank. This helps to diminish the switching activity on the clock network, thereby decreasing dynamic power consumption within the design. Due to the fact the translation accomplished via the synthesis tool is solely combinational; it is referred to as combinational clock gating. This transformation does not alter the behavior of the register being gated.
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