Computing-in-memory (CIM) is a promising approach to reduce latency and improve the energy efficiency of the multiply-and-accumulate (MAC) operation under a memory wall constraint for artificial intelligence (AI) edge processors. This paper proposes an approach focusing on scalable CIM designs using a new ten-transistor (10T) static random access memory (SRAM) bit-cell. Using the proposed 10T SRAM bit-cell, we present two SRAM-based CIM (SRAM-CIM) macros supporting multibit and binary MAC operations. The first design achieves fully parallel computing and high throughput using 32 parallel binary MAC operations. Advanced circuit techniques such as an input-dependent dynamic reference generator and an input-boosted sense amplifier are presented. Fabricated in 28 nm CMOS process, this design achieves 409.6 GOPS throughput, 1001.7 TOPS/W energy efficiency, and a 169.9 TOPS/mm 2 throughput area efficiency. The proposed approach effectively solves previous problems such as writing disturb, throughput, and the power consumption of an analog to digital converter (ADC). The second design supports multibit MAC operation (4-b weight, 4-b input, and 8-b output) to increase the inference accuracy. We propose an architecture that divides 4-b weight and 4-b input multiplication to four 2-b multiplication in parallel, which increases the signal margin by 16× compared to conventional 4-b multiplication. Besides, the capacitive digital-to-analog converter (CDAC) area issue is effectively addressed using the intrinsic bit-line capacitance existing in the SRAM-CIM architecture. The proposed approach of realizing four 2-b parallel multiplication using the CDAC is successfully demonstrated with a modified LeNet-5 neural network. These results demonstrate that the proposed 10T bit-cell is promising for realizing robust and scalable SRAM-CIM designs, which is essential for realizing fully parallel edge computing.INDEX TERMS computing-in-memory, static random access memory, deep neural network, machine learning, edge processor. * value when technology scaling factor is used. ** result when CONV1 and FL7 layers are implemented in the SRAM-CIM.
Objective: An understanding of functional interhemispheric asymmetry in ischemic stroke patients is a crucial factor in the designs of efficient programs for post-stroke rehabilitation. This study evaluates interhemispheric synchronization and cortical activities in acute stroke patients with various degrees of severity and at different post-stroke stages. Approach: Twenty-three patients were recruited to participate in the experiments, including resting-state and speed finger-tapping tasks at week-1 and week-3 post-stroke. Multichannel near-infrared spectroscopy (NIRS) was used to measure the changes in hemodynamics in the bilateral prefrontal cortex (PFC), the supplementary motor area (SMA), and the sensorimotor cortex (SMC). The interhemispheric correlation coefficient (IHCC) measuring the synchronized activities in time and the wavelet phase coherence (WPCO) measuring the phasic activity in time-frequency were used to reflect the symmetry between the two hemispheres within a region. The changes in oxyhemoglobin during the finger-tapping tasks were used to present cortical activation. Main results: IHCC and WPCO values in the severe-stroke were significantly lower than those in the minor-stroke at low frequency intervals during week-3 post-stroke. Cortical activation in all regions in the affected hemisphere was significantly lower than that in the unaffected hemisphere in the moderate-severe stroke measured in week-1, however, the SMC activation on the affected hemisphere was significantly enhanced in week-3 post-stroke. Significance: In this study, non-invasive NIRS was used to observe dynamic synchronization in the resting-state based on the IHCC and WPCO results as well as hemodynamic changes in a motor task in acute stroke patients. The findings suggest that NIRS could be used as a tool for early stroke assessment and evaluation of the efficacy of post-stroke rehabilitation.
Objective. Non-invasive brain stimulation has been promoted to facilitate neuromodulation in treating neurological diseases. Recently, high-definition (HD) transcranial electrical stimulation and a novel electrical waveform combining a direct current (DC) and theta burst stimulation (TBS)-like protocol were proposed and demonstrated high potential to enhance neuroplastic effects in a more-efficient manner. In this study, we designed a novel HD transcranial burst electrostimulation device and to preliminarily examined its therapeutic potential in neurorehabilitation. Approach. A prototype of the transcranial burst electrostimulation device was developed, which can flexibly output a waveform that combined a DC and TBS-like protocol and can equally distribute the current into 4 × 1 HD electrical stimulation by automatic impedance adjustments. The safety and accuracy of the device were then validated in a series of in vitro experiments. Finally, a pilot clinical trial was conducted to assess its clinical safety and therapeutic potential on upper-extremity rehabilitation in six patients with chronic stroke, where patients received either active or sham HD transcranial burst electrostimulation combined with occupational therapy three times per week for four weeks. Main results. The prototype was tested, and it was found to comply with all safety requirements. The output parameters were accurate and met the clinical study needs. The pilot clinical study demonstrated that the active HD transcranial burst electrostimulation group had greater improvement in voluntary motor function and coordination of the upper extremity than the sham control group. Additionally, no severe adverse events were noted, but slight skin redness under the stimulus electrode immediately after stimulation was seen. Conclusions. The results demonstrated the feasibility of incorporating the HD electrical DC and TBS-like protocol in our device; and the novel neuromodulatory device produced positive neurorehabilitation outcomes in a safe fashion, which could be the basis for the future clinical implementation for treating neurological diseases. Trial registration: ClinicalTrials.gov Identifier: NCT04278105. Registered on 20 February 2020.
To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2VDSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µVrms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.
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