We presented ModulAr Semantic CAching fRAmework (MASCARA) that deployed Semantic Caching (SC) to perform a fast query processing based on Field Programmable Gate Arrays (FPGAs) accelerators. In addition of the accelerators, cache management plays an important role to address coalescing strategy and replacement policy so as to maximize the performance of FPGA caching. Therefore, in this paper, we present a coalescing heuristic with a new replacement function that leverages advantages of traditional strategies and overcomes their drawbacks. The proposed heuristic reduces response time, improves data availability, and saves cache space with respect to the semantic locality of query workload.
COALESCING IN MASCARA-FPGAWe presented the SC concept and prototype of 12]. If we have 𝑁 data region 𝐷𝑅 and the answer of an incoming query 𝑄 overlaps them, the result could be the formation of 2𝑁 + 1 new 𝐷𝑅, where 𝑁 + 1
The use of Field Programmable Gate Arrays (FPGA) has become attractive in recent years to accelerate database analysis. Meanwhile, Semantic Caching (SC) is a technique for optimizing the evaluation of database queries by exploiting the knowledge and resources contained in the queries themselves. Organizing SC on FPGA is relevant in terms of response time and quality of results to increase system performance. To make SC scalable on FPGAs, we have proposed a ModulAr Semantic CAching fRAmework (MAS-CARA) in which relevant stages or modules could be convertible as accelerators on FPGAs. Therefore, in this paper, we aim to present a complementary query processing platform based on the cooperation model between MASCARA and FPGA. This novel approach extends the advantage of the classical SC, which is mainly based on Central Processing Unit (CPU), by offloading computationally intensive phases to FPGA. Moreover, MASCARA-FPGA presents the workflow of query rewriting and partial query execution in a pipelined execution model where multiple accelerators can run in parallel. In our experiments, the Query Trimming can reduce the response time by up to 3.96 times with only one accelerator used.
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