The industrial fabrication process of silicon heterojunction (SHJ) solar cells can induce locally depassivated regions (so-called defectivity) because of transportation steps (contact with belts, trays, etc.) or simply the environment (presence of particles at the wafer surfaces before thin film deposition). This surface passivation spatial heterogeneity is gaining interest as it may hinder the SHJ efficiency improvements allowed by incremental process step optimizations. In this paper, an experimentally supported simulation study is conducted to understand how the local a-Si:H/c-Si interface depassivation loss impacts the overall cell performance. The defectivity-induced cell performance drop due to depassivated regions was attributed to a bias-dependent minority carrier current flow towards the depassivated region, which is shown to affect all current-voltage (I(V)) parameters, and in particular the fill factor. Simulation was used further in order to understand how the defectivity properties (spatial distribution, localization and size) impact the induced performance losses. In the light of all results, we propose ways to mitigate the defectivity influence on the cell performances.
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