This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface-and thin-SOI microstructures that included microcavities, RF switches and various accelerometers. Advantages of our technique are its versatility, smaller footprint, reduced chip thickness and process complexity, post-CMOS batch processing capability and added functionality due to the possibility of integrating additional electrodes for MEMS. Besides fabrication details, this work also discusses related design aspects for large-area MEMS and demonstrates the encapsulation results. Successfully encapsulation of device geometries as large as 955x827.m2 has been achieved.
Attractive material properties of plasma enhanced chemical vapour deposited (PECVD) silicon carbide (SiC) when combined with CMOS-compatible low thermal budget processing provides an ideal technology platform for developing various microelectromechanical systems (MEMS) devices and merging them with integrated circuits. In this paper we present a generic surface micromachining technology developed using a stressoptimised PECVD SiC as the structural and encapsulation material for MEMS. An overview of selected MEMS applications realised, at DIMES Technology Center (DTC) of TU Delft, using the PECVD SiC surface micromachining technology is provided. Presented MEMS examples include-a pressure sensor, wafer-level thin-film packaging, RF switch and accelerometers. Potential applications for the presented technology include automotive, industrial and medical systems, where devices are often subjected to harsh environments.Keywords Silicon carbide (SiC) Á Microelectromechanical systems (MEMS) Á Micromachining Á Pressure sensor Á Accelerometer Á RF switch Á Wafer-level packaging (WLP) Á Thin film encapsulation (TFE)
We present a simple, flexible and low cost MEMSfabrication process, developed using deep reactive ion etching (DRIE) and wafer bonding technologies, for manufacturing in-plane high aspect ratio (HAR) inertial sensors. Among examples, the design and fabrication results of a two axis inertial device are presented. Fabricated device thickness ranged up to 140 1m and a HAR of28 was obtained. Compared to the existing approaches reported in literature, the salient features of the presented process are: single-sided single-wafer processing using just two lithographic masks, capability to fabricate standalone MEMS as well as CMOS compatible MEMS post-processing via process variations, the use of plasma etching for wafer thinning that facilitates stictionless dry-release of MEMS, and its suitabilityfor batch processing.1. Introduction HAR micromachining of silicon enabled by DRIE technology [1] has led to the development of low cost and high performance inertial microsensors for various applications in the automotive, consumer, medical, aerospace and defense systems. By effectively exploiting the vertical dimension, such sensors exhibit better mechanical properties due to the use of single crystal silicon, a thicker proof mass that reduces the mechanical noise and improves the sensitivity, smaller form-factor and a relatively larger output capacitance leading to a higher performance than the surface micromachined devices. This paper presents a simple MEMS process flow that has been used for fabricating various in-plane capacitive HAR inertial sensors such as accelerometers and gyroscopes. Also the design and simulation of a dual axis inertial device is described that is later fabricated using the presented technological approach.
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