This article describes a new strategy for controlling the tilt angle and side‐lobe level of linear array antennas by using a genetic algorithm. A very simple fitness function for controlling the performance of the array was constructed and is suggested. Simulations show excellent results for directing the main lobe and side‐lobe levels. © 2002 Wiley Periodicals, Inc. Microwave Opt Technol Lett 33: 12–14, 2002; DOI 10.1002/mop.10215
Integrated current sensing circuits intended for Smart-Power and embedded applications featuring galvanic isolation are implemented. They are based on magnetic detection using the CMOS compatible split-drain transistor (MAGFET) that provides a very linear output current versus magnetic field. Two approaches are used to generate the magnetic field. The Coil approach and the Strip approach. In the first one the current to be sensed flows through an integrated coil placed atop the split-drain transistor and produces a relatively strong magnetic coupling enough to cause a detectable current. The second approach features an array of 126-paralleled split-drain transistors along a metal strip intended to carry higher current levels. Both techniques were realized as integrated current sensors built in 0.35 m CMOS technology. The calculated and measured sensitivities were around 1μA/A and 0.75μA/A for the Coil and Strip approaches respectively. For a typical single split-drain bias current of 50μA, the minimum detectable current within 1Hz are 2.8 A/ Hz and 42 A/ Hz for the Coil and Strip approaches respectively. The Strip can carry currents up to 500mA, whereas the flowing current in the Coil is limited to 20mA. Thus, the choice is based on the resolution and sensing current level of the application.
Integrated current-sensing circuits intended for smart-power and embedded applications featuring galvanic isolation are implemented. They are based on magnetic detection using a CMOS-compatible split-drain transistor that provides a very linear output current versus magnetic field. Two approaches are used to generate the magnetic field: the coil approach and the strip approach. In the first, the current to be sensed flows through an integrated coil placed atop the split-drain transistor and produces a magnetic coupling strong enough to cause a detectable current. The second approach features an array of 126 paralleled split-drain transistors placed along a metal strip intended to carry higher current levels. Both techniques were realized as integrated current sensors built in 0.35 µm CMOS technology. The calculated and measured sensitivities were around 1 and 0.75 µA/A for the coil and strip approaches, respectively. For a typical single splitdrain bias current of 50 µA, the minimum detectable currents within 1 Hz are 2.8 and 42 µA/ √ Hz for the coil and strip approaches, respectively. The strip can carry currents up to 500 mA, whereas the flowing current in the coil is limited to 20 mA. Thus, the choice is based on the resolution and sensing current level of the application.Index Terms-Current measurement, noise correlation, split drain.
In the last years the gate-oxide overstress has become a great concern for CMOS circuits and even more so for circuits such as charge pumps. A new charge pump circuit that overcomes the gate-oxide overstress problem and has improved efficiency is proposed in this work. Simulations have shown that for 1μA current load a four-stage structure of proposed circuit reaches efficiency of about 64%, what is almost three times the efficiency of previous solutions in the same conditions. The better efficiency makes this circuit more suitable for low-power applications. Measurements have shown that a four-stage structure of the new circuits yields a pumping efficiency of 98.12%.Index Terms-charge pump, reliability, low power, overstress INTRODUCTIONCharge pumps are circuits devised to provide voltage higher than that of the power supply. They are applied traditionally in the operation of flash and EEPROM memories and nowadays in systems embedding MEMS devices. The Dickson structures [1] are the most popular but suffer of poor pumping efficiency caused by the increasing of the threshold voltage due to the body effect of the NMOS transistors. Moreover as the voltage difference between each stage reaches 2Vdd these structures suffer from gate-oxide overstress.The gate-oxide overstress has become a great concern for charge pump circuits [5] as the gate-oxide thickness is scaled down. This problem greatly reduces the lifetime of MOS devices according to [7]. In the last few years some charge pump structures that overcome this problem have been proposed [3] [4]. Nevertheless the previous solutions have poor efficiency mainly for low current load conditions, due to the multiple phases of clock they need to operate. A new charge pump structure free from gate-oxide overstress and more efficient than the previous solutions is proposed in this work. (a) (b) Figure 1: (a) New charge pump circuit, (b) Four-stage structureThe better efficiency of the proposed structure lies in the fact that it needs only two phases to operate, together with a clock voltage doubler that is also free from gateoxide overstress.In section 2 a description of the proposed structure is given. Results that demonstrate the performance of the circuit are presented in section 3, followed by conclusions in section 4. DESCRIPTION OF THE CIRCUIT The Charge Pump CircuitThe proposed charge pump circuit presented in figure 1(a) works as follows. CKP is in phase with CK but has a doubled peak voltage. While CK is high, node A is low switching on M4, M6 and M8. In this phase CKP is also high and node D will reach the voltage of node B switching off M2. As M8 is on C4 will charge the next stage or else the output.
A 10-bit, 80-kS/s charge-redistribution successive approximation analog-to-digital converter is presented, which incorporates a novel stray capacitance compensation technique that is appropriate for low-power design in order to accomplish input voltage offset reduction. Three different versions of the ADC were fabricated in 0.35µ µ µ µm, 4M2P standard CMOS process. The compensation mechanism implemented in one of the ADC versions proved its effectiveness by showing an input voltage offset that is circa 60 times smaller than what was measured in the other two uncompensated versions. Also from fabricated samples of the compensated ADC, measured values for INL and DNL are 0.47 LSB and 0.58 LSB, respectively. Operating at 3.3V at the nominal speed, the offset-compensated ADC consumes 122µ µ µ µW.
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