The memory effect of a trilayer structure (rapid thermal oxide/Ge nanocrystals in SiO2/sputtered SiO2) was investigated via capacitance versus voltage (C–V) measurements. The Ge nanocrystals were synthesized by rapid thermal annealing of the cosputtered Ge+SiO2 films. The memory effect was manifested by the hysteresis in the C–V curve. Transmission electron microscope and C–V results indicated that the hysteresis was due to Ge nanocrystals in the middle layer of the trilayer structure.

Articles you may be interested inCharge retention enhancement in stack nanocrystalline-Si based metal-insulator-semiconductor memory structure Appl.Annealing temperature dependence of capacitance-voltage characteristics in Ge-nanocrystal-based nonvolatile memory structures J. Appl. Phys. 99, 036101 (2006); 10.1063/1.2168249 Conduction mechanisms and charge storage in Si-nanocrystals metal-oxide-semiconductor memory devices studied with conducting atomic force microscopy J. Appl. Phys. 98, 056101 (2005); 10.1063/1.2010626 Investigation of Ge nanocrytals in a metal-insulator-semiconductor structure with a Hf O 2 ∕ Si O 2 stack as the tunnel dielectric Appl. Phys. Lett. 86, 113105 (2005); 10.1063/1.1864254Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal-insulator-semiconductor structure

No abstract

Trilayer structures, consisting of a rapid thermal oxide (RTO) layer (2.5 or 5 nm thick) grown on silicon, a sputtered Ge middle layer (3–20 nm thick), and a 50-nm-thick sputtered silicon oxide capping layer, exhibit significant penetration of Ge atoms into the silicon substrate for devices with the smaller (2.5 nm) RTO thickness, resulting in negligible nanocrystal formation and hence no charge storage or memory effect. The Ge penetration is minimized by replacing the RTO layer with a high dielectric constant (high-κ) silicon nitride/hafnium dioxide stack (grown by metalorganic chemical vapor deposition) having a larger physical thickness but smaller equivalent oxide thickness of 1.9 nm. Results show that the high-κ trilayer structure exhibits better charge storage capability (in terms of a lower program voltage) and better charge retention performance as compared to the RTO trilayer structure.