In this paper, a highly efficient interinterpolation architecture for the H.264/AVC standard is proposed. Since the placement order of frame pixels in the memory is either row-wise or columnwise which may not be suitable for the sample prediction in particular direction, this paper proposes a novel interpolator design which can dynamically configure the data-path for different predicted modes to perform proper computation schedules suitable for the nature input order of reference samples. The proposed design methodology not only can avoid the additional data transposition buffer, but most importantly the data transfer time spent to fetch the reference samples can be overlapped with the data computation time. Furthermore, by decomposing the chroma interpolation into a series of shift and addition operations, both luma and chroma interpolations can be integrated within the same module. In addition to the data-path design, this paper also proposes a new data-reuse buffer design based on a two-dimensional cache architecture to explore the possible data reuse among the inter and intra partitions. This design can be easily integrated with the H.264 interpolator to reduce the enormous demand of memory access. Our experimental results shows that our saving of memory bandwidth can be 23% more than what the best design can achieve by exploring the intrapartition data reuse only. The proposed design methodology has been implemented, and the result shows that the proposed interpolation architecture is the most compact design among the literatures which can perform the real-time H.264 video decoding with resolution up to 1920脳1088 high-definition television standard. The proposed interpolator can be applied to the dedicated H.264 hardware codec design for various consumer devices.
For a VSAT system to be competitive in the ever increasingly sophisticated world of telecommunication industries, a new and more efficient VSAT system which requires much lesser satellite EIRP but with very little increase in the cost of the earth terminal than the present system requirements is desirable.This can be conveniently achieved by concatenating the half-rate convolutional code used in the existing VSAT system with an outer Reed-Solomon (RS) code system as recommended by the Consultative Committee for Space Data Systems (CCSDS). This paper describes one of the cheapest and best practical means of implementing this RS code using the new AT&T DSP16A processor to meet the customer data rate of 64 kbi t/s.In the effort to search for a competitive way of promoting the VSAT system in the UK, a new efficient VSAT system is proposed which will give a 3dB improvement in EbAio over the present system [l].The idea behind this 3dB improvement is that, put very simply, a 9.6 kbit/s channel data rate could be doubled to 19.2 kbit/s (ignoring the coding 'overheads') whilst still using the same satellite power: or alternatively one can have the choice of transmitting say two 64 kbit/s bearers in say one 114 transponder as in one of the INTELNET service packages offered by INTELSAT, thus halving the space segment charges. Reduction in the space segment charges under this new proposed system, however, can only be justified if the resulting increase in the total costs of the earth terminals installed for all the subscribers served in the system is less than the corresponding reduction obtained. The 3dB gain in Ebmo relative to the half-rate, constraint length seven convolutional encoded system used in the present VSAT system can be achieved in several ways [l]. The Consultative Committee for Space Data Systems (CCSDS) has recommended a concatenated code system which was originally intended for the deep space missions application [a]. This code system can achieve an approximately close to 3dB improvement in its performance relative to the mentioned half-rate convolutional code with the expense of a slight drop in the total code rate efficiency to 44X. This has been perceived to be the best approach for the new VSAT system since the implementation only concerns the development of the RS codec to be concatenated to the existing codec thus keeping the increase in earth terminal cost to the minimum possible. The required RS codec has been successfully implemented using the special purpose GF1 tm Decoders [ 3 ] , [4] and VLSI circuits [5] achieving operating speed to 120 Mbit/s. Whilst the special purpose IC's or VLSI circuits design for the RS codec can be used for the new VSAT system, the cost of the codec could be substantial when only moderate number of them are mufactured.Since the customer data rate served by the present VSAT system is in the range 9.6 to 64 kbit/s, the a1 ternative implementation using the general purpose DSP processor is worth looking into. The implementation of a very short RS codec (block length of 15...
This paper presents an edge-list compression scheme for the two-dimensional (2D) graphic systems. To fill a 2D graphic object described by complex curve paths, either enormous global edge-table has to be created, or a more economic line-based edgelist can be utilized. The latter approach, however, will sacrifice the rendering quality by approximating the curve using straightlines. Therefore, this paper proposes a new edge-list structure, which first divides each path of the object into several upward and downward segments. Each segment will then be coded based on the difference vector of neighboring pixels, and the quadrant this vector belongs to. The entire path can be converted into a compact bit-stream. To decode the bit-stream, an additional linklist structure has to be built, which contains the direct access links to the entry points in the bit-stream in order to fetch the local lowest points to produce an active edge-list for each scan line. Our preliminary results show that the proposed scheme can reduce the overall edge-table size by an average factor of 15.
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