Fully-printed temperature sensor arrays—based on a flexible substrate and featuring a high spatial-temperature resolution—are immensely advantageous across a host of disciplines. These range from healthcare, quality and environmental monitoring to emerging technologies, such as artificial skins in soft robotics. Other noteworthy applications extend to the fields of power electronics and microelectronics, particularly thermal management for multi-core processor chips. However, the scope of temperature sensors is currently hindered by costly and complex manufacturing processes. Meanwhile, printed versions are rife with challenges pertaining to array size and sensor density. In this paper, we present a passive matrix sensor design consisting of two separate silver electrodes that sandwich one layer of sensing material, composed of poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS). This results in appreciably high sensor densities of 100 sensor pixels per cm$$^2$$ 2 for spatial-temperature readings, while a small array size is maintained. Thus, a major impediment to the expansive application of these sensors is efficiently resolved. To realize fast and accurate interpretation of the sensor data, a neural network (NN) is trained and employed for temperature predictions. This successfully accounts for potential crosstalk between adjacent sensors. The spatial-temperature resolution is investigated with a specially-printed silver micro-heater structure. Ultimately, a fairly high spatial temperature prediction accuracy of 1.22 °C is attained.
The recent renaissance in machine learning is requesting computing power at an everincreasing rate. In order to meet this demand, tensor processing units (TPU) are becoming popular because they hold the promise to be more efficient in terms of power usage as well as throughput compared to GPUs. This is achieved by integrating a huge number of matrix-multiply units (MMU) to perform a massive amount of parallel multiply-accumulate operations. However, this causes excessive localized hot-spots. Elevated on-chip temperatures jeopardize reliability and significantly reduce the lifetime of semiconductor devices by accelerating aging defects. Therefore, it is vital to obtain accurate thermal maps of the TPU die at the design time to ensure reliability requirements during the run-time. Due to the high power density, traditional forced air convection cooling is often insufficient. Hence, liquid cooling may seem promising, but it requires substantial maintenance effort. To overcome this challenge, novel cooling concepts need to be explored. Recent advances in thermoelectric coolers (TEC), more specifically ultra thin-film superlattice thermoelectric (TE) devices, have opened new doors to combat this obstacle. To this end, finite-element (FEM) simulations enable designers to find tradeoffs between temperature and cooling cost. However, such multi-physics simulations are extremely time-consuming, which prevents designers from exploring the available design-space. In this work, we demonstrate a neural network (NN) model that captures the effects of a superlattice TEC device mounted on top of a TPU die. The additional required cooling cost is also estimated. The commercial multi-physics tool ANSYS® is employed in order to obtain high resolution data towards training the NN model. Our NN model allows to speed up the design-space exploration considerably, reducing the time required to generate a single thermal map from, on average, 45 min in ANSYS® to merely 70 ms with an average prediction error of 0.26°C. Our model covers a wide range of design parameters, such as convection film coefficient, power density and superlattice TEC cooling intensity.Open Source Release: Upon acceptance, we will make our framework including the generated thermal map dataset as well as all trained NN models publicly available.
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