Due to the Multiple Input Multiple Output technology, applied in wireless communication, where a transceiver has to deal with multidimensional channels, the QR-decomposition is an often used preprocessing algorithm, especially for the design of iterative tree search detection algorithms. In this paper we introduce an efficient FPGA implementation of a QR-decomposition algorithm, which is designed for a MIMO detector developed in view of the Long Term Evolution (LTE). The proposed architecture is based on a line-by-line systolic array structure and reaches the peak matrix throughput, which is required to achieve the defined LTE peak data rate of a 2 × 2 MIMO constellation using a 20 MHz transmission bandwidth. In this paper we describe the architecture and FPGA implementation of the algorithm in detail and show the performance results of a Xilinx Virtex IV realization.
Iterative tree search algorithms like K-Best or sphere decoder algorithms are promising candidates for the upcoming wireless communications systems. In this paper a square root and division free Givens rotation (SDFG) algorithm is merged into a common sphere decoder algorithm to decrease the entire complexity. Furthermore, the algorithm is speeded up due to parallelizing the computation by taking the orthogonality of the real and imaginary parts of the complex transmit symbols into account.
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