Phone: (5 12) 420-9273Austin, TX Tempe, A 2 ABSTRACT A previously validated detailed model of a 119-pin Flip-Chip Plastic Ball Grid Array (FC-PBGA) package was created and validated against experimental data for natural convection and forced coirvection environments. Next, two compact models were derived, a two-resistor model (created using the JEDECstandard based computational approach), and a multi-resistor model (created using the DELPHI optimization approach that was boundary condition independent within engineering accuracy). The compact models were placed in natural convection and forced convection (velocities of 1 and 2 m/s) environments with and without a heatsink. Based on the agreement obtained between the detailed model and compact model simulations, the accuracy and validity of the two compact models was assessed. Of the two compact thermal models considered, the Delphi multi-resistor model provided the same predictive estimates (within 5 % ) as simulations involving a detailed thermal model of the package in natural and forced convection environments both with and without attached heatsinks. Some thermal modeling issues were addressed with respect to implementation of compact thermal models with attached heatsinks. IN TR 0 D U CTIO NCreating validated thermal models of electronic packages has always been a challenge in the electronics industry. Existing metrics such as junction-to-case thermal resistance and junction-to-am bient thermal resistance are sometimes useful as figures of merit, but have proven to fail spectacularly in many real environments (Dutta [l]). This is because these measures typically are reported for ill-defined boundary conditions, and are also by definition subject to large variations depending on the environment.In order to improve the ability of design engineers to model electronic parts successfully, project DELPHI (Development of Physical models for an Integrated design environment) was launched in 1993 by several European end-users with the specific aim of creating a methodology for the generation of thermal models that would be independent of the environmental boundary conditions (Rosten and Lasance [2]). This project has produced an established methodology for creation of two types of thermal modelsa "detailed" model (representing the package in sufficient geometric detail so as to capture all relevant thermal paths accurately; KEY WORDS: electronic package, component-leve] thermal and a "compact" model (a much reduced model consisting of a thermal resistance network that would still capture the thermal behavior of the parts accurately, and predict die-junction temperatures to a high behavioral model; air cooling; plastic ball grid array; compact model, thermal resistance NOMENCLATURE Therm a1 conductivity, (W/[m KI) k P Power, (W)
Temperature, strength, and stress at the Dash thin neck of large diameter silicon crystals during Czochralski growth are analyzed. The combination stress from the crystal weight, the meniscus weight, and the surface tension are calculated for the initial crystal growth stage, including shoulder portion and the first 12.5 cm long of body growth. Two shoulder lengths, 2.5 and 10 cm with three diameter sizes, 200, 250, and 300 mm are calculated. A two-dimensional, axisyrnmetric heat conduction model using a commercially available software, ANSYS"." is used to calculate the temperature distribution in the crystals. The strength of the thin neck is obtained from the relationship between the upper yield strength of silicon and temperature. To maintain a dislocation-free (DH) lattice structure, the strength of the thin neck must be higher than the combination stress acting upon the thin neck. The results indicated that the neck temperature increases with the crystal diameter and decreases with the shoulder length. The minimum neck diameter to maintain a DF structure for a 200 rnrn crystal is 3.7 mm with a 2.5 cm shoulder and 3.06 mm with a 10 cm shoulder. For a 250 mm crystal, the minimum neck diameter is 4.8 mm with a 2.5 cm shoulder and 4.1 mm with a 10 cm shoulder. For a 300 mm diameter crystal, the minimum neck diameter is 6.1 mm with a 2.5 cm shoulder and 5.2 mm with a 10 cm shoulder.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 128.218.248.200 Downloaded on 2015-04-12 to IP Process and Device Center, Dallas, TX 75243. Present address: National Semiconductor Corporation, Santa microscopy (STM),*." transmission electron microscopy Clara, CA 95052. (TEM),ll-l5 and x-ray diffraction (XRD),'"17 have been Present address: Hitachi, Ltd., Tokyo 185, Japan. employed t o investigate the effect o f thermal oxidation on ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 128.218.248.200 Downloaded on 2015-04-12 to IP
In discrete radio frequency (RF) microelectromechanical systems (MEMS) packages, MEMS devices were fabricated on silicon or galium arsenide (GaAs) chips. The chips were then attached to substrates with die attach materials. In wafer-level MEMS packages, the switches were manufactured directly on substrates. For both types of packages, when the switches close, a contact resistance of approximately 1 exists at the contact area. As a result, during switch operations, a considerable amount of heat is generated in the minuscule contact area. The power density at the contact area could be up to 1000 times higher than that of typical power amplifiers. The high power density may overheat the contact area, therefore affect switch performance and jeopardize long-term switch reliabilities.In this paper, thermal analysis has been performed to study the heat dissipation at the switch contact area. The goal is to control the "hot spots" and lower the maximum junction temperature at the contact area. A variety of chip materials, including Silicon, GaAs have been evaluated for the discrete packages. For each chip material, the effect of die attach materials has been considered. For the wafer-level packages, various substrate materials, such as ceramic, glass, and low-temperature cofire ceramic (LTCC) have been studied. Thermal experiments have been conducted to measure the temperature at the contact area and its vicinity as a function of dc and RF powers. Several solutions in material selection and package configurations have been explored to enable the use of MEMS with chips or substrates with relatively poor thermal conductivity. For discrete MEMS packages, placing the die inside a copper cavity on the substrate provides significant heat dissipation. For wafer-level packages, thin diamond coatings on the substrate could reduce the hot-spot temperature considerably.
The Plastic Ball Grid Array (PBGA) package attracts considerable interest, being one of the most promising packaging technologies of the moment. Thermal analysis of a package and a Printed Circuit Board (PCB) stack-up is performed for a better understanding of package constitutive elements, allowing an enhanced thermal coupling of package and board for cost effective thermal management. A commercial Computational Fluid Dynamics (CFD) software was applied for thermal simulation. The study focuses on detailed thermal modeling of a 256 Wirebonded PBGA (depopulated bump array) package in a natural convection setup. The model was refined to include all the features, and the calculated junction-toambient thermal resistance for each simulation was compared to available experimental data. The order of creating the internal structures in the model has a strong impact on the package thermal characteristics. The calculated errors varied from 5% (detailed model) to 43% (simplified model).
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