Indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) gated with sputtered silicon dioxide dielectric were fabricated. Under different sputtering pressures of silicon dioxide, the device is able to produce transfer curves from clockwise hysteresis to anticlockwise hysteresis, corresponding to different operation modes and thus adding complementary performance by the same material system and device structure. In the interface trapping mode, the transistor exhibited inhibitory synaptic spiking behavior induced by positive stimuli. In the electric doublelayer coupling mode, positive stimuli led to excitatory synaptic spiking behavior, while negative stimuli resulted in inhibitory synaptic spiking behavior. All the transistor and synaptic spiking behaviors are conducted within ±1 V range. Enriched functionality and ultralow operation voltage make sputtered SiO 2 -gated IGZO TFTs promising candidate for neuromorphic applications. Index Terms-1 V, oxide thin-film transistor (TFT), synaptic spiking behavior, synaptic transistor. I. INTRODUCTION T HIN-FILM transistors (TFTs) based on electrolyte gate dielectric have drawn particular attention in recent years, mainly due to their potential neuromorphic applications in brain-inspired computation beyond the traditional von Neumann architecture [1], [2]. Electrolyte is ion-conducting but electron-insulating material. In electrolyte-based TFTs, a positive gate voltage causes ion migration and accumulation at theManuscript

applications. Various types of synaptic plasticity behaviors have been demonstrated, including spiking-width-dependent plasticity, spiking-height-dependent plasticity, and spiking-rate-dependent plasticity, etc. [18][19][20][21][22][23][24][25][26] In biosystems, the modulation of synaptic weight often results from the alteration of the number of neurotransmitters. Meanwhile, the transmission of signals is always continuous rather than intermittent. As a result, a previous signal event which caused a temporal disturbance of the neurotransmitter will no doubt have an effect on the plasticity during later signal events. While the plasticity of the weights refers to synaptic plasticity behaviors, the plasticity of plasticity itself refers to synaptic metaplasticity behaviors. [27] Metaplasticity, which endows synapse the history-dependent or experienced learning characteristics, plays an important role in underlying mechanisms for memory and learning functions. [28] In recent years, synaptic metaplasticity behaviors have been successfully emulated on different types of memoristors. [29][30][31][32][33][34][35] Electrolyte-gated transistor (EGT) is a type of new-concept transistors that utilize electrolyte dielectric, which enables ionconducting while maintaining electron-insulating. [36] Under applied gate voltage bias, mobile ions migrate to the electrolyte/ semiconductor interface, mirroring a layer of electrons within the semiconductor channel and hence modulating the channel conductance. [37,38] The unique ion-mediated conductance modulation makes it ideal for mimicking the neurotransmittermediated synaptic weight modulation because ions are also the carrier in brain neuro functions. [39][40][41][42][43][44] EGTs with various types of electrolytes were studied for mimicking synaptic metaplasticity behaviors. John et al. emulated homeostatic synaptic metaplasticity behaviors on 2D transition metal di-chalcogenide (MoS 2 ) transistors gated with ion liquids. [45] Wen et al. studied the activity-dependent synaptic plasticity behaviors in indiumtin-oxide transistors with plasma-enhanced chemical-vapordeposition deposited phosphorosilicate glass electrolytes. [46] Ren et al. studied the threshold-tunable, spike-rate-dependent plasticity behaviors on similar devices. [47] Guo et al studied emulated the Bienenstock-Cooper-Munro learning rule with tunable threshold on indium-tin-oxide transistors gated with λ-Carrageenan electrolytes. [48] Jiang et al. emulated metaplasticity behaviors on dual in-plane gates indium-zinc-oxide transistors gated with chitosan electrolytes. [49] However, previous research of synaptic metaplasticity behaviors on EGTs were Electrolyte-gated transistors have been proposed as promising candidates for neuromorphic applications. Synaptic plasticity behaviors and most recently synaptic metaplasticity or plasticity of plasticity behaviors have been mimicked on electrolyte-gated transistors. In this work, indium-gallium-zinc-oxide thin-film transistors gated with sputtered SiO 2 electrolytes are fa...

The human brain is capable of short- and long-term memory with retention times ranging from a few seconds to several years. Electrolyte-gated transistors have drawn attention for their potential to mimic synaptic behaviors in neuromorphic applications, but they generally operate at low voltages to avoid instability and, hence, offer limited tunability. Sputtered silicon dioxide electrolytes are utilized in this work to gate indium-gallium-zinc-oxide thin-film transistors, which offer robust operation at much higher voltages. The synaptic memory behavior is studied under single and multiple pulses and under mild (1 V) and strong stimuli (up to 8 V). The devices are found to be capable of providing an extremely wide range of memory retention time from ∼2 ms to ∼20 000 s, over seven orders of magnitude. Furthermore, based on the experimental data on individual transistors, pattern learning and memorizing functionalities are conceptually demonstrated.

Temperature has always been considered as an essential factor for almost all kinds of semiconductor-based electronic components. In this work, temperature-dependent synaptic plasticity behaviors, which are mimicked by the indium–gallium–zinc oxide thin-film transistors gated with sputtered SiO 2 electrolytes, have been studied. With the temperature increasing from 303 to 323 K, the electrolyte capacitance decreases from 0.42 to 0.11 μF cm –2 . The mobility increases from 1.4 to 3.7 cm 2 V –1 s –1 , and the threshold voltage negatively shifts from −0.23 to −0.51 V. Synaptic behaviors under both a single pulse and multiple pulses are employed to study the temperature dependence. With the temperature increasing from 303 to 323 K, the post-synaptic current (PSC) at the resting state increases from 1.8 to 7.3 μA. Under a single gate pulse of 1 V and 1 s, the PSC signal altitude and the PSC retention time decrease from 2.0 to 0.7 μA and 5.1 × 10 2 to 2.5 ms, respectively. A physical model based on the electric field-induced ion drifting, ionic–electronic coupling, and gradient-coordinated ion diffusion is proposed to understand these temperature-dependent synaptic behaviors. Based on the experimental data on individual transistors, temperature-modulated pattern learning and memorizing behaviors are conceptually demonstrated. The in-depth investigation of the temperature dependence helps pave the way for further electrolyte-gated transistor-based neuromorphic applications.

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