Intestinal perfusion with carbohydrates inhibits gastric emptying via vagal and spinal capsaicin-sensitive afferent pathways. The aim of the present study was to determine the role of 1) 5-hydroxytryptamine (5-HT)(3) receptors (5-HT(3)R) in mediating glucose-induced inhibition of gastric emptying and 2) 5-HT(3)R expression in vagal and spinal afferents in innervating the duodenum. In awake rats fitted with gastric and duodenal cannulas, perfusion of the duodenum with glucose (50 and 100 mg) inhibited gastric emptying. Intestinal perfusion of mannitol inhibited gastric emptying only at the highest concentration (990 mosm/kgH(2)O). Pretreatment with the 5-HT(3)R antagonist tropisetron abolished both glucose- and mannitol-induced inhibition of gastric emptying. Retrograde labeling of visceral afferents by injection of dextran-conjugated Texas Red into the duodenal wall was used to identify extrinsic primary afferents. Immunoreactivity for 5-HT(3)R, visualized with an antibody directed to the COOH terminus of the rat 5-HT(3)R, was found in >80% of duodenal vagal and spinal afferents. These results show that duodenal extrinsic afferents express 5-HT(3)R and that the receptor mediates specific glucose-induced inhibition of gastric emptying. These findings support the hypothesis that enterochromaffin cells in the intestinal mucosa release 5-HT in response to glucose, which activates 5-HT(3)R on afferent nerve terminals to evoke reflex changes in gastric motility. The primary glucose sensors of the intestine may be mucosal enterochromaffin cells.
Accurate and efficient simulation of large parallel applications can be facilitated with the use of direct execution and parallel discrete-event simulation. This paper describes MPI-SIM, a direct execution-driven parallel simulator designed to predict the performance of existing MPI and MPI-IO application. MPI-SIM can be used to predict the performance of these programs as a function of architectural characteristics, including number of processors, message communication latencies, caching algorithms, and alternative implementations of collective I/O operations. Results are presented, which show the use of MPI-SIM in performing a scalability study of real-world applications. The benchmarks chosen for the study include Sweep3D, one of the ASCI benchmarks, and BTIO, an I/O-intensive benchmark from the NAS Parallel Benchmark suite. MPI-SIM is shown to accurately and efficiently predict the performance of Sweep3D running on an Origin 2000. It is also used to demonstrate the impact of the number of I/O nodes on BTIO’s performance.
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