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This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

Vertedores de parede delgada são estruturas hidráulicas simples, baratas e úteis na medição de vazão em condutos livres. Embora seja fácil a obtenção do valor de vazão quando conhecidas as dimensões do vertedor, o problema inverso é mais complexo: dimensionar um vertedor para uma vazão máxima esperada, pois para tal é necessária a resolução de uma equação com incógnita de graus 3/2 e 5/2, que não se pode executar analiticamente, requerendo-se o uso de recursos computacionais. O presente trabalho objetivou apresentar e disponibilizar à comunidade acadêmica e aos profissionais da área de Hidráulica o VertCalc: um software offline e gratuito que possui funções de estimativa de vazão e de dimensionamento de vertedores com geometrias retangular com ou sem contrações, triangular e trapezoidal. O programa foi desenvolvimento na linguagem Visual Basic e se apresentou como de fácil usabilidade e com confiabilidade dos resultados quando comparados com a literatura técnica. A análise de erros de estimativas dos valores do programa desenvolvido resultou em percentuais entre 0,0% e 6,6%.

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This work studies the effects of the temperature variation, from 300K to 500K, on the electrical parameters of SOI n-type and p-type junctionless nanowire transistors. The temperature influence on the threshold voltage, subthreshold slope, and the effective carrier mobility were analyzed. The mobility scattering mechanisms were analyzed and show that nanowire devices have the phonon scattering as their major component, although there is a significant component of the ionized impurity scattering that can be identified as well. These electrical parameters were also analyzed for short channel devices with a channel length of 40nm. P-type devices showed higher degradation with the temperature as the doping concentration is higher than n-type devices.

This work analyzes the effects of the fin height on the electrical parameters of junctionless transistors through experimentally calibrated 3-D simulations. Results show that for long channel devices the better compromise is obtained with higher fin height, with higher ION/IOFF and smaller values of SS and DIBL, whereas for short channel ones the better compromise is found with smaller fin height, due to the reduced SS and DIBL and increased ION/IOFF ratio.