T he Java programming language promises portable, secure execution of applications. Early Java implementations relied on interpretation, leading to poor performance compared to compiled programs. Compiling Java programs to the native machine instructions provides much higher performance. Because traditional compilation would defeat Java's portability and security, another approach is necessary. This article describes some of the important issues related to just-in-time, or JIT, compilation techniques for Java. We focus on the JIT compilers developed by Sun for use with the JDK (Java Development Kit) virtual machine running on SPARC and Intel processors. (Access the Web at www.sun. com/workshop/java/jit for these compilers and additional information.) We also discuss performance improvements and limitations of JIT compilers. Future Java implementations may provide even better performance, and we outline some specific techniques that they may use.
The Sun Network Software Environment ("SE) is a network-based object manager for software development. The NSE supports parallel development through an optimistic concurrency control mechanism, in which developers do not acquire locks before modifying objects. Instead, developers copy objects, modify the copies, and merge the modified objects with the originals. Objects managed by the NSE are typed, and the set of types can be extended by tool builders. The NSE is designed to work with heterogeneous implementations and poor communication.
The Sun Network Software Environment (NSE) is a network-based object manager for software development. The NSE supports parallel development through an optimistic concurrency control mechanism, in which developers do not acquire locks before modifying objects. Instead, developers copy objects, modify the copies, and merge the modified objects with the originals. Objects managed by the NSE are typed, and the set of types can be extended by tool builders. The NSE is designed to work with heterogeneous implementations and poor communication. 154 0 1989 ACM 0270-5257/89/05OO/Ol54$00.75 Recommended by: Mark Dowson
We present an overview of the design of a machine-code-level, global (intraprocedural) optimizer that supports several front-ends producing code for the Hewlett-Packard Precision Architecture family of machines. The basic optimization strategy is described, including information about the division of responsibilities between various components of the compiler.Optimization algorithms are described, including a discussion of the dataflow information they require. Measurements showing the collective and individual effects of various optimizer components are presented.The performance data presented here was collected using a preliminary version of the optimizer. Development is continuing and further improvements are expected. The SettingThe HP Precision Architecture defines a machine with a simple register-based instruction set using 32 general-purpose registers.2 3 Only load and store instructions reference memory. The architecture acknowledges the use of pipelined hardware by defining branches to not take effect until the second instruction cycle following the branch. Referencing the target of a load instruction in the instruction which follows the load will result in a one-instruction hardware interlock.
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