BACKGROUND: Parkinson's disease (PD) is a neurodegenerative disease that predominantly alters patients' motor performance. Reduced step length and inability of step are important symptoms associated with PD. Assessing patients' motor state monitoring step length helps to detect periods in which patients suffer lack of medication effect. OBJECTIVE: Evaluate the adaption of existing step length estimation methods based on accelerometer sensors to a new position on left lateral side of waist in 28 PD patients. METHODS: In this paper, a user-friendly position, the lateral side of the waist, is selected to place a tri-axial accelerometer. A newly developed step detection algorithm -Sliding Window Averaging Technique (SWAT) is evaluated in detecting steps using signals from this location. The detected steps are then used to estimate step length using four proposed correction factors for Zijlstra's, Gonzalez's and Weinberg's methods that were originally developed for the signals from lower back. RESULT: Results obtained from 28 PD patients are discussed and the effects of calibrating in each motor state are compared. A generic correction factor is also proposed and compared with the best method to use instead of individual calibration. Despite variable gait speed and different motor state, SWAT achieved overall accuracy of 96.76% in step detection. Among the different step length estimators, the Zijlstra method performs better with multiplying individual correction factors that consider left and right step length separately providing average error of 0.033 m. CONCLUSIONS: Zijlstra's method with individual correction factor that considers left and right step length separately and obtained from during ON state of a PD patients provide most accurate estimation among the others. As training session is during ON state, data from induced OFF state to train the methods are not required. A generic correction factor is also proposed to apply with Zijlstra's method to avoid individual calibration process.
Circuit partitioning plays an important role in physical design automation of very large scale integration (VLSI) chips. In this brief we present a new connectivity based top down as well as bottom up approach to clustering algorithm for VLSI circuit partitioning. The proposed clustering algorithm partitions the circuit by focusing on highly interconnected cell groups. This clustering algorithm leads to a parallel implementation in which multiple processors are used to identify clusters simultaneously. The process starts with forming clusters by grouping the cells that are tightly connected and as well as the cells that are loosely connected. Considering both types of groups has the advantage that clusters formed from this technique will be highly connected and compact too. Therefore the proposed clustering method can reduce the size and also speed-up the large-scale partitioning problem without loosing partitioning solution qualities. The performance of the proposed clustering algorithm is evaluated on a standard set of partitioning benchmark-ISPD98 benchmark suite.
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