ALD tungsten nitride (WN) becomes attractive for CMOS contact liner/barrier application because of its highly conductive and conformal film properties. Due to the distinct differences in its process nature from the traditional PVD processes, a full optimization from film properties to process integration is necessary for the 65nm CMOS device fabrication. This paper highlights the issues and shows the approaches to address these issues in implementing the ALD WN process for the CMOS contact application.
Tunnel field-effect transistor (TFET) is a promising device which has extraordinary performance on subthreshold swing and is feasible for ultralow power applications. However, one of the main factors of power dissipation and circuit delay among different designs of TFET, namely, parasitic capacitances, has not been discussed in detail. In this paper, parasitic capacitance of various types of TFETs are simulate and analyze.
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