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Phase change materials (PCMs) provide a high energy density for thermal storage systems but often suffer from limited power densities due to the low PCM thermal conductivity. Much like their electrochemical analogs, an ideal thermal energy storage medium combines the energy density of a thermal battery with the power density of a thermal capacitor. Here, we define the design rules and identify the performance limits for rationally-designed composites that combine an energy dense PCM with a thermally conductive material. Beginning with the Stefan-Neumann model, we establish the material design space using a Ragone framework and identify regimes where hybrid conductive-capacitive composites have thermal power densities exceeding that of copper and other high conductivity materials. We invoke the mathematical bounds on isotropic conductivity to optimize and define the theoretical limits for transient cooling using PCM composites. We then demonstrate the impact of power density on thermal transients using copper inverse opals infiltrated with paraffin wax to suppress the temperature rise in kW cm−2 hotspots by ∼10% compared to equivalent copper thin film heat spreaders. These design rules and performance limits illuminate a path toward the rational design of composite phase change materials capable of buffering extreme transient thermal loads.

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The increasing complexity and power density of electronic systems have necessitated the development of thermal circuits that can not only remove but actively redirect the flow of heat. Passive thermal regulators are promising as heat routing components that can mitigate large temperature spikes by transitioning between high and low resistance states without external actuation. Existing regulators, however, are often either limited to fixed temperature regulation ranges due to solid-state material property limitations or are difficult to package in a compact form factor. Here, we present a passive, compact (1 × 1 cm2 active area), and tunable thermal regulator that functions based on the dynamics of vapor transport through a noncondensable gas cavity. The device demonstrates a switching resistance ratio of 4 in response to variations in the input power ranging from approximately 0.6 W to 14 W. The device is also able to set the temperature difference across the hot and cold sides to a fixed, “clamped” value that is reasonably independent of heat flow. Both the overall resistance and the clamped temperature difference can be easily tuned by presetting the pressure of the noncondensable gas. We present a brief analysis of the physical operating principles of the device and lay the groundwork for the development of future passive and tunable thermal circuitry components.

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As electronic device power densities continue to increase, vapor chambers and heat pipes have emerged as effective thermal management solutions for hotspot mitigation. A crucial aspect of vapor chamber functionality depends on the properties of the microporous wick that drives heat and mass transport within the device. While many prior studies have focused on the optimization of these porous structures to increase the maximum capillary-limited dryout heat flux, an equally important aspect of porous wick design is the minimization of the thermal resistance above heated areas. Segmented wicks with geometries that vary along the length of the wick are attractive candidates that can potentially be used to fulfill these simultaneous design goals. Previous studies on bisegmented wicks with only two distinct adiabatic and heated region geometries, however, have shown mixed results regarding the degree of performance benefit over homogeneous wicks. In this work, we present a systematic modeling approach to investigate the optimal composition of segmented micropillar wicks comprising multiple, discrete regions of graded geometry. Using a genetic algorithm, we generate Pareto fronts of optimal segmented wick distributions that maximize the dryout heat flux and minimize the thermal resistance for a given heating configuration. We find that optimal, graded segmented wicks are capable of dissipating dryout heat fluxes more than 200% higher than baseline homogeneous wicks with significantly lower thermal resistance. The sensitivity of the wick performance to the total number of geometry segments is found to vary depending on the desired heat flux and thermal resistance operating regimes.

This paper reviews recent progress in the development of silicon-based vapor chambers for heat spreading in electronic packages. Effective hotspot mitigation is an increasingly challenging issue in electronics thermal management, and the use of silicon vapor chambers creates opportunities for thermal-expansion matched, high performance heat spreaders that can be directly integrated with the semiconductor die. While silicon micro heat pipes have been extensively studied as one-dimensional heat transport mechanisms for heat routing in semiconductor substrates, silicon vapor chambers require special consideration and different manufacturing approaches due to the different heat transport configurations involved. The following review therefore provides an overview on the evolution of silicon vapor chambers in terms of fabrication strategies and performance characterization. Particular focus is given to opportunities and challenges associated with using silicon as the vapor chamber envelope material rather than more traditional metal-based vapor chambers, such as the ability to optimize the wick geometry with greater fidelity and issues with manufacturing scalability.

Advances in manufacturing techniques are inspiring the design of novel integrated microscale thermal cooling devices seeking to push the limits of current thermal management solutions in high heat flux applications. These advanced cooling technologies can be used to improve the performance of high power density electronics such as GaN-based RF power amplifiers. However, their optimal design requires careful analysis of the combined effects of conduction and convection. Many numerical simulations and optimization studies have been performed for single cell models of microchannel heat sinks, but these simulations do not provide insight into the flow and heat transfer through the entire device. This study therefore presents the results of conjugate heat transfer CFD simulations for a complex copper monolithic heat sink integrated with a 100 micron thick, 5 mm by 1 mm high power density GaN-SiC chip. The computational model (13 million cells) represents both the chip and the heat sink, which consists of multiple inlets and outlets for fluid entry and exit, delivery and collection manifold systems, and an array of fins that form rectangular microchannels. Total chip powers of up to 150 W at the GaN gates were considered, and a quarter of the device was modeled for total inlet mass flow rates of 1.44 g/s and 1.8 g/s (0.36 g/s and 0.45 g/s for the quarter device), corresponding to laminar flow at Reynolds numbers between 19.5 and 119.3. It was observed that the mass flow rates through individual microchannels in the device vary by up to 45%, depending on the inlet/outlet locations and pressure drop in the manifolds. The results demonstrate that full device simulations provide valuable insight into the multiple parameters that affect cooling performance.