A production-compatible method for the correction of image-placement (IP) error over a 1x stencil mask as used for proximity electron lithography (PEL) has been demonstrated. The mask IP error as measured using a newly developed metrology tool was fed forward to the PEL stepper, LEEPL-3000 and corrected for via the fine deflection of the electron beam. The overlay errors with respect to the substrate patterned by the ArF scanner have decreased from 63.6/59.3 nm to 26.1/36.4 nm in the x/y directions, but they are still larger than the errors of 15.2/14.8 nm for the conventional feedback method. Therefore, some improvements in the metrology method, the mask chucking method, the mask flatness and so on are required.
Electron projection lithography mask format layer stress measurement and simulation of pattern transfer distortion J. Vac. Sci. Technol. B 20, 3053 (2002); 10.1116/1.1521732Patterning-induced image placement distortions on electron beam projection lithography membrane masks Low-energy electron projection lithography (LEEPL) is a candidate for next generation lithography and thus the 1ϫ LEEPL mask requires a stringent local image placement (IP) error budget. Applying a doping method with silicon-on-insulator substrates, 700-nm-thick membranes were investigated for stress control and in-plane distortion (IPD), which are the main contributors to local IP errors. Stress control results show that at a dopant concentration of 6.74ϫ 10 19 /cm 3 , the membrane stress in a 10 mm test structure is 8.4 MPa. Also stress variation is excellent at 0.3 MPa across a 200 mm complementary stencil mask on support strut-type LEEPL mask. The IPD results indicate that small membrane window size, low void fraction, as well as low membrane stress is the proper strategy to allow a stencil mask with dense stencil patterns to meet required IPD. Additionally, the local IP errors of large scale integrated 90 nm hole pattern were demonstrated.
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