We report on the fabrication of top-gate phototransistors based on a few-layered MoS(2) nanosheet with a transparent gate electrode. Our devices with triple MoS(2) layers exhibited excellent photodetection capabilities for red light, while those with single- and double-layers turned out to be quite useful for green light detection. The varied functionalities are attributed to energy gap modulation by the number of MoS(2) layers. The photoelectric probing on working transistors with the nanosheets demonstrates that single-layer MoS(2) has a significant energy bandgap of 1.8 eV, while those of double- and triple-layer MoS(2) reduce to 1.65 and 1.35 eV, respectively.

The evolution of copper-based interconnects requires the realization of an ultrathin diffusion barrier layer between the Cu interconnect and insulating layers. The present work reports the use of atomically thin layer graphene as a diffusion barrier to Cu metallization. The diffusion barrier performance is investigated by varying the grain size and thickness of the graphene layer; single-layer graphene of average grain size 2 ± 1 μm (denoted small-grain SLG), single-layer graphene of average grain size 10 ± 2 μm (denoted large-grain SLG), and multi-layer graphene (MLG) of thickness 5-10 nm. The thermal stability of these barriers is investigated after annealing Cu/small-grain SLG/Si, Cu/large-grain SLG/Si, and Cu/MLG/Si stacks at different temperatures ranging from 500 to 900 °C. X-ray diffraction, transmission electron microscopy, and time-of-flight secondary ion mass spectroscopy analyses confirm that the small-grain SLG barrier is stable after annealing up to 700 °C and that the large-grain SLG and MLG barriers are stable after annealing at 900 °C for 30 min under a mixed Ar and H2 gas atmosphere. The time-dependent dielectric breakdown (TDDB) test is used to evaluate graphene as a Cu diffusion barrier under real device operating conditions, revealing that both large-grain SLG and MLG have excellent barrier performance, while small-grain SLG fails quickly. Notably, the large-grain SLG acts as a better diffusion barrier than the thicker MLG in the TDDB test, indicating that the grain boundary density of a graphene diffusion barrier is more important than its thickness. The near-zero-thickness SLG serves as a promising Cu diffusion barrier for advanced metallization.

We report on the nanosheet-thickness effects on the performance of top-gate MoS(2) field-effect transistors (FETs), which is directly related to the MoS(2) dielectric constant. Our top-gate nanosheet FETs with 40 nm thin Al(2)O(3) displayed at least an order of magnitude higher mobility than those of bottom-gate nanosheet FETs with 285 nm thick SiO(2), benefiting from the dielectric screening by high-k Al(2)O(3). Among the top-gate devices, the single-layered FET demonstrated the highest mobility of ∼170 cm(2) V(-1) s(-1) with 90 mV dec(-1) as the smallest subthreshold swing (SS) but the double- and triple-layered FETs showed only ∼25 and ∼15 cm(2) V(-1) s(-1) respectively with the large SS of 0.5 and 1.1 V dec(-1). Such property degradation with MoS(2) thickness is attributed to its dielectric constant increase, which could rather reduce the benefits from the top-gate high-k dielectric.

Nanosheet transistors based on mechanically exfoliated MoS 2 and other transition metal dichalcogenide layers have already been reported demonstrating good device performances. In an approach to synthesize a large area two-dimensional (2D) sheet, chemical vapor deposition methods were reported and the transfer of those sheets onto other arbitrary substrates was also attempted, although studies on the direct imprinting of such 2D semiconductor sheets are rare. Here, we report on a direct imprinting method, the polydimethylsiloxane (PDMS)-adopting approach, that enables the fabrication of patterned bottom-gate MoS 2 nanosheet field-effect transistors (FETs) on any substrate; using direct printing methods MoS 2 FETs were successfully fabricated on glass. Since our FETs were also controlled to be a depletion or an enhanced mode with the modulated MoS 2 thickness on a patterned bottom-gate, our imprinting approach is regarded as a meaningful advance toward 2D nanosheet electronics.