In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus based system while satisfying given end-to-end real-time constraints of the entire system such as throughput and latency constraints. In this paper, we define a bus scenario representing a set of possible execution sequences of tasks and bus transfers executed in a bus based system. Then we propose a method for deriving real time budgets of all the tasks running in parallel and pipelined fashion from the pair of a system configuration (such as bus topology) and a bus scenario. In deriving such real time budgets, we consider computational complexity of each task, the amount of bus transfers and bus arbitration policies (e.g. fixed priority or time divided round robin based arbitration). We show that the proposed method is effective for designing several bus based systems such as MPEG decoders.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
customersupport@researchsolutions.com
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.