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Parasitic inductance in printed circuit board (PCB) geometries can detrimentally impact the electromagnetic interference (EMI) performance and signal integrity of high-speed digital designs. This paper identifies and quantifies the parameters that affect the inductance of some typical PCB geometries. Closedform expressions are provided for estimating the inductances of simple trace and ground plane configurations. Index Terms-Electromagnetic coupling, electromagnetic interference, inductance I. INTRODUCTION T HE parasitic inductance, capacitance, and resistance of traces, vias, and planes on a printed circuit board (PCB) are important at high frequencies for modeling electromagnetic interference (EMI) and susceptibility processes. These parasitics comprise the effective noise source mechanism and coupling path of an integrated circuit (IC) source to an unintentional "antenna," which can result in an EMI or susceptibility problem. Parasitic inductance in PCB geometries is often the most difficult parameter to quantify. The concepts of inductance and partial inductance play a key role in PCB modeling. The inductance of the signal path is an important parameter in high-speed signal integrity calculations. Delta-I noise modeling, crosstalk calculations, and common-mode noise-source identification all rely on good estimates of the inductance associated with traces, vias, and signal return paths on PCB's. Equivalent circuit models of EMI processes at the board level for geometries known to lead to problems that exceed regulatory limits are desirable at the design stage for estimating radiated emissions. A useful model includes an effective noise source, and the parasitics (inductance, capacitance, and resistance) that comprise the coupling path of the noise-source to the EMI antenna. This equivalent circuit can then be used together with a known or suspected EMI antenna and a fullwave solution of Maxwell's equations to estimate radiation.

A simple kinetic model has been developed for the electrodeposition of normalCdTe and other 12–16 (II–VI) or 13–15 (III–V) compounds from solutions containing reducible ions of both constituents and is based upon a generalized Butler‐Volmer equation that considers ion transport limitations near the cathode. Although the deposition itself is a non‐equilibrium process, the reaction between the plated cadmium and tellurium is assumed sufficiently rapid that any infinitesimally small volume in the deposit remains in quasi‐chemical equilibrium, as defined by the equilibrium constant‐mass action expression involving the activities of the solid constituents and conservation of mass, as invoked by a unity mole fraction sum. Exponential activity coefficients are postulated consistent with “regular” solution models. Although neglecting second‐order effects such as hydrogen generation, IR and space‐charge voltage drops within the deposit, and possible phase segregation, the model yields a convenient algorithm to numerically simulate voltammetric (j‐E) curves and calculate the mole fractions and activities of cadmium, tellurium, and cadmium telluride existing at the deposit surface for any deposition potential.