For PBLOCOS, pits often form on buffer polysilicon after nitride removal and on silicon substrate after polysilicon removal; a mechanism is formulated based on experimental results to explain the pits formation. Also, the twin-white-ribbon effect is explored in PBLOCOS as opposed to the single-white-ribbon effect in conventional LOCOS. Device performance from PBLOCOS and LOCOS have been collected and compared. PBLOCOS results in bird's beak length, about 0.25 ~m per side, only half of that from LOCOS. It is demonstrated that PBLOCOS is as good as conventional LOCOS in terms of device performance.In the last decade, microelectronics fabrication has evolved through a dramatic change, especially the shrinkage in circuit dimensions. The evolution was primarily due to improvement in stepper resolution and fabrication technologies. However, the isolation technologies do not seem to be able to keep up with the ever-decreasing device geometry. For years, LOCOS has been the mainstream method for device isolation. The main drawback with the conventional LOCOS, the existence of a long bird's beak length (BBL), is the main obstacle for conventional LOCOS to be used in the submicron and sub-half-micron device fabrication.In general, an ideal isolation technique should meet the following requirements (1): First, spacing between active areas should be minimal. Second, BBL should be as small as possible. Third, leakage current between active devices must be negligible. Fourth, the process of the isolation formation should not adversely affect the process parameters required for active device fabrication. Finally, the isolation process should be easy to implement and control.For years, many efforts have focused on reducing BBL; to mention a few, SILO, SWAMI, PHOTOX, and TRENCH techniques have all been claimed successful. Sealed-interface local oxidation (SILO) (2), an improvement over conventional LOCOS, employs a thin layer of nitride underneath the pad oxide to seal off the lateral diffusion of oxidants, hence reducing the BBL, but the use of this layer often leads to excessive stress. The SWAMI (3) technique is able to reduce BBL and achieve an isoplanar surface simultaneously. However, SWAMI is much more complicated than conventional LOCOS as Si recess etching and nitride sidewall are required; furthermore, it is difficult to control defect formation.PBLOCOS (4-8) uses a layer of polysilicon between oxide and nitride to absorb excessive stress resulting from thicker nitrides being used. Consequently, 50% reduction in BBL can be achieved. Ghezzo et al. (9) and Guldi et al. (10) optimized the PBLOCOS stacked layer thicknesses with factorial experiments and characterized the electrical performances for their 0.8 ~m CMOS process. PBLOCOS (i) BEFORE ETCHING NITRIDE POLY -SI PAD OXIDE SI (ib AFTER ETCHING NITRIDE POLY -SI PAD OXIDE SI Fig. 1. The architecture of PBLOCOS. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 128.122.253.212 Downloaded on 2015-...
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