The performance of application processors for cellular phones is greatly improved. Moreover, next generation cellular phones will support complex CPU applications as well as media applications, e.g., rich Java applications and sophisticated user interfaces. The conventional approach to achieve higher performance is increasing clock frequency; however this causes several serious problems including increased power consumption, an increased relative memory response cycle and design complexity using deeper pipeline structures. To overcome these difficulties, a triple-CPU application processor chip and a parallel communication library is developed which provides a fully compatible application interface on a single processor. It enables a reduction in software development cost with enough CPU performance. In this paper, several techniques to enlarge memory throughput and reduce power consumption to meet the various needs for active and idle time are described. Figure 7.5.1 shows a block diagram of this chip, which integrates three ARM926 cores (Processing Element PE0-2), DSP, graphic accelerators, 640KB SRAM, an SDRAM interface and other intellectual properties (IPs). Each IP is connected by 32b Multilayer AHB. There are several multi-CPU embedded processors [1]- [3]. A heterogeneous multiprocessor structure using conventional CPU, DSP and a standard bus protocol is adopted to reduce hardware and software development costs. Most IPs are written in a C-based language and synthesized by Cyber [4].Three techniques to enlarge memory bandwidth are shown in Fig. 7.5.2. The first is allocating four AHBs for one SDRAM I/F to meet different demands from different IPs. In general, the CPU does not require higher memory bandwidth but faster response to minimize the cache-miss penalty; in contrast, media processing requires large bandwidth. Each IP is categorized into two groups: latency sensitive and throughput respective. The former is connected to AHB0 or 3 and the others are connected to AHB1 or 2. Because lower bus occupation of AHB0/3 reduces bus collisions among the former IPs, this technique gives a shorter memory response cycle even when executing rich multi-media applications.The second technique is quad bus interfaces with read/write buffers. A read buffer keeps all eight words of SDRAM response. If the succeeding access hits the data, it is provided from the buffer without SDRAM access. A write data is held in a write buffer temporarily to release AHB immediately and merge a succeeding write data if possible. These functions reduce response time and SDRAM access. Third technique is access scheduling. The scheduler arbitrates among 4-read and 3-write requests from quad bus interfaces considering priority and SDRAM state. Many access candidates enlarge scheduling possibilities to maximize throughput.Figure 7.5.3 shows the simulated performance. The left graph shows the relationship between read latency and SDRAM traffic; the right graph the performance impact of SDRAM traffic. This impact is compared to a JPEG benchmark ...

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This paper proposes a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXKSSC DSP cores. The SPXKSSC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to cvaluate the overall performance of target LSls on real workloads before actual LS1 fabrication, sofhvare simulators arc too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSls integrated with a SPXKSSC DSP core in order to evaluate the overall performance of audioivideo CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA should he suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating perfonnance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described.