A chip level redundant self-checking fail-safe microprocessor has been developed using a 0.35 pm CMOS embedded gate array. The microprocessor integrates two synthesizable processor cores and a self-checking comparator in a single chip. A full-custom processor core was transformed into each of the synthesizable cores for this purpose. Design methodologies suitable for reusing synthesizable processor cores has also been developed. Developed synthesizable processor cores and design methodologies reduce the cost of process migration of the chip. Migrating to the newer process improves the performance of the developed microprocessor with low development cost.

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It is a common practice to realize the internal control of a logic LSI by means of a microprogramming method. A high‐speed operation of this logic LSI requires a highspeed ROM (micro ROM) which stores this microprogram code. This paper proposes a new circuit configuration derived from a combination of bipolar and CMOS technology for a high‐speed micro ROM. In this configuration, the memory cell array is made of MOS transistors while the array periphery consists of a bipolar/CMOS composite circuit in which a high driving capability and a large gm of the bipolar transistor are used so that a high degree of integration and a high speed are attained simultaneously. To confirm the high‐speed characteristic of the proposed circuit, a micro ROM of 2 k words x 64 bits has been fabricated with the 2 μm Hi‐BiCMOS process mixing the bipolar and CMOS structures. The test results of the fabricated device have a minimum read‐out cycle time of 16 ns which is more than twice that of a CMOS circuit having an identical configuration.