Same program can be written in different programming languages and different ways. One programming language will have advantages and disadvantages compared to another; hence sometimes it is needed to rewrite the code into another language to support this or that functionality. This paper demonstrates an algorithm of interlanguage translator, which is using intended machine learning (ML) algorithms to ensure higher translation rate. In the scope of research, tool for interlanguage translation is created and tested with two programming languages: Python and Java. Comparison results for translation accuracy are calculated, about 53% without AI algorithms and about 65% with the use of AI algorithms.
This paper presents a power consumption estimation algorithm for static analysis. IR drop is being calculated for each separated node, which makes this algorithm favorable for IR drop calculation on infinite power network. The power consumption is being calculated using random walk algorithm, which includes Monte Carlo simulation method for increasing accuracy of estimation. For power mesh with 150 k power nodes, total IR drop calculation takes 152.17 seconds.
Designs including tens of millions of standard cells in one chip are commonly used in current IC projects, so finding optimal location on a chip surface for each logic cell is a very important step in IC design. Apart from finding room for logic cell placement with minimum chip area, length of connecting wires is also playing big role and needs to be taken under control. In this paper, research and implementation of standard cell placement-optimizations' quadratic algorithm is described. Main research is on runtime and wire length. For 5K standard cells, algorithm implementation takes 83 second.
This algorithm integrates second level Built in self-test (BIST) into multiple memory grouping wrapper. Second level BIST brings additional reliability into the memory system while fastening testing time. Main approach is to test whole memory modules from top level by numerous step count of which can be modified based on power consumption requirement and overheat conditions. The worst case of the algorithm can be observed by the time when the number of steps is equal to the number of memory modules, otherwise the testing time will be relative to 1/N (N is the number of steps). The main advantage of memory wrapping methodology is the possibility of increasing variety of the number of bits and the number of cells in the memory, while using limited memories provided by foundry.
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