Ultrasensitive, label-free, and real-time prostate-specific antigen (PSA) sensor was developed using n-type silicon nanowire-based structures configured as field-effect transistors using the conventional “top-down” semiconductor processes. Specific binding of PSA with antibody of PSA (anti-PSA) immobilized on the Si surface through covalent linkage leads to a conductivity change in response to variations of electric field at the surface. The conductance changes depending on PSA concentrations and pH values in solution according to isoelectric point of PSA provide the evidence of the real-time detection of 1fg∕ml PSA. The authors also explored the sensitivity of PSA immunodetection depending on both Si–field-effect transistors (FET) dimensions and doping concentrations to provide strategy for fabrication of an ultrasensitive Si-FET biosensor.
Abstract:This paper investigates what kinds of choices exist in determining the voting structure for cascaded triple modular redundant (TMR) modules, how to identify efficient voting structures, and the effects of voting structures on the overall system reliability. While the classic single-voter and three-voter architectures have been used for about fifty years, the paper shows that there are more practically useful voting structures which provide efficient trade-offs between hardware overhead and system reliability. Specifically, a single-voter architecture with the voter fanout of one is found to be more reliable than the classic single-voter architecture for a reasonably wide range of component reliability. Keywords: cascaded triple modular redundant (TMR) modules, voting structure, hardware overhead, reliability, recovery distance Classification: Science and engineering for electronics References[1] J. V. Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," in Automata Studies, ed. C. E. Shannon and
An efficient recovery method for thread-level speculation (TLS) is proposed. The method tracks the inter-thread data dependence as a method for identifying those threads that are obviously unaffected by a data dependence violation. The method is simple to implement. Still, the simulation results using benchmark applications show that the method can significantly reduce the number of unnecessary thread restarts and consequently improve the performance of TLS. Specifically, when compared with the baseline TLS, TLS with the proposed method is 2.3 times faster for IS, 1.7 times faster for equake, and 3.5 times faster for mcf with the use of 64 cores. With the method, the performance of TLS increases steadily up to 64 cores for IS, equake, and mcf, while the speedup of the baseline TLS starts to saturate at 8 or 16 cores.
Abstract:The way-predicting (WP) cache is simple and energyefficient when used as L1 cache. However, a concern in the WP cache is the speed of the slow hit. This paper proposes the use of way-lookup buffer (WLB) cache to alleviate the problem of slow hit in the WP cache. The results show that the WLB slow hit is 33% faster than the WP slow hit in L1 cache. This is important because the slow hit is often the critical path that determines the processor clock cycle time. The WLB cache is as energy-efficient as the WP cache when used as L1 cache; using the WLB cache can reduce the power consumed by the conventional L1 cache by 68%. Therefore, if we like the nice properties (i.e., simplicity and energy efficiency) of the WP cache but are reluctant to use it because the slow hit extends the processor clock cycle time, then the WLB cache is the one to use.
The use of a rollback buffer (RB) for hiding the rollback latency in logbased eager hardware transactional memory is proposed. The RB allows a transaction to abort without performing rollback, but still makes the transaction's old values immediately available. In effect, the rollback latency almost disappears. When running the Stanford transactional applications for multi-processing benchmark on a 16core processor that implements the LogTM-SE, the speedup (decrease in execution time) achieved with a 2 KB RB is 15.8% on average.
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