The design of a feedback equalizer (FE) in Multi-level Decisiofi Feedback Equalization (MDFE) for magnetic recording channels is presented. The fully digital feedback equalizer is implemented with a look-up-table based architecture. The FE has 11 taps where the past decisions are stored and subsequently used to determine the feedback coefficients. With the insertion of a single pipeline, two clock periods are allowed for the completion of the critical timing loop. The improvement in throughput is made possible with the application of look-ahead computation. Based on a 0.35-pm CMOS technology, the post-layout simulation results show that the FE is capable of operating at a clock rate of 132MHz under the typical conditions.
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