This paper presents a high speed Si bipolar transistor using polysil icon sidewall base-elect]-ode transistor (POSET) technology developed from selfaligned silicon bipolar transistor technology. We reduced the parasi tic capacitance between the base and the collector to a minimum to maximize the transistor's speed. Other techniques were usecl to make a practical device with a gate delay time of 21.5 ps/gate at a switching current of 0.32 mA. This is faster than any commercial bipolar transistor at a switching current about one third.The low-resistance technology greatly increased the grain size of amorphous silicon and optimized the impurity density. This minimized the disadvantages of POSET and allowed us to reduce the parasitic capacitance between the base and the collector. The advantages of POSET were all maintained.We also used the technologies above to make an ECL circuit. The ECL circuit combined a graded collector profile, a shallow base produced by 20 keV B F z + ion injection, and U-grooved element isolation. The characteristics of the bipolar transistors we produced are described later. We also compare the characteristics with those of ESPER transistors [4 1 [5 I. I NTRODW I ON The delay of an ECL gate composed of Si bipolar transistors is now below 25 picoseconds [11[23.Transistors this fast must have very low parasitic capacitance and parasitic resistance and the cutoff frequency fT must be high. Our latest transistor has reduced capacitance between the base and col lector because of its small base area, and this reduces parasitic capacitance. To do this, we used a selfalignment technology, called POSET, which we developed from conventional self-aligned transistor technology. POSET is characterized by a polysilicon sidewall on the side of the aperture which forms a part of the base leading electrode. This gives a small base area almost equal to the aperture area. We produced a self-al igned bipolar transistor with a base aperture 0.5 ,um wide.Conversely, POSET reduces both the base and emitter aperture widths, and also reduces the base leading electrode width because of the narrow polysi I icon sidewall electrodes. This increases the emi t t er and base paras i t i c resistances.POSET was combined with embedding tungsten in the emitter aperture to reduce emitter parasitic resistance [31. Low-resistance polysilicon based leading electrode technology was also used to reduce the base resistance. Fig. 1 shows a cross-sectional SEM image of the POSET transistor with polysi 1 icon embedded U-grooved element isolation. Fig. 2 is an enlarged SEM image of the base and emitter of the POSET transistor. We formed the POSET transistor on a silicon epitaxial layer 1.0 urn thick and with a resistivity of 2.0Qcm. This transistor has a lower layer oxide film, a p+ polysilicon film, and an upper layer oxide film on the epitaxial layer. The epitaxial layer is exposed by an aperture in a field oxide film. We formed all base areas, including the internal and external bases, inside the 0.5 B m aperture that passes through...
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