Greater I/O density at the die level, coupled with more demanding performance requirements, is driving the need for improved wiring density and a concomitant reduction in feature sizes for electronic packages. Traditionally, greater wiring densities are achieved by reducing the dimensions of vias, lines, and spaces, increasing the number of wiring layers, and utilizing blind and buried vias. However, each of these approaches possesses inherent limitations, for example those related to drilling and plating of high aspect ratio vias, reduced conductance of narrow circuit lines, and increased cost of fabrication related to additional wiring layers. One method of extending wiring density beyond the limits imposed by these approaches is a strategy that allows for metal-to-metal z-axis interconnection of subcomposites during lamination to form a composite structure. Conductive joints can be formed during lamination using an electrically conductive paste. As a result, one is able to fabricate structures with verticallyterminated vias of arbitrary depth. Replacement of conventional plated through holes with vertically-terminated vias opens up additional wiring channels on layers above and below the terminated vias, enables die shrink, and eliminates via stubs which cause reflective signal loss. In addition, parallel lamination of testable subcomposites offers yield improvement, shorter cycle times, and ease of incorporating features conducive to high speed data rates. As a case study, an example of a z-axis interconnect construction for a flip-chip plastic ball grid array package with a 150 3m die pad pitch is given. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.

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The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

The wide range of applications for medical electronics drives unique requirements that can differ significantly from commercial & military electronics. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. Advanced microelectronics packaging solutions with embedded passives are enabling SWaP reductions. Implementation of these solutions has realized up to 27X reduction in physical size for existing PWB assemblies, with significant reductions in weight. Shorter interconnects can also reduce or eliminate the need for termination resistors for some net topologies. Successful miniaturized products integrate the following design techniques and technologies: component footprint reduction, thin high density interconnects substrate technologies, I/O miniaturization and IC assembly capabilities. This paper presents fabrication and electrical characterization of embedded actives and passives on organic multilayered substrates. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on embedded chips, resistors, and capacitors. Embedded passive technology further enhances miniaturization by enabling components to be moved from the surface of the substrate to its internal layers. The use of thin film resistor material allows creating individual miniaturized buried resistors. These resistors provide additional length and width reduction with negligible increases to the overall substrate and module (SiP) height. Resistor values can vary from 5 ohm to 50 Kohm with tolerances from 5 to 20% and areas as small as 0.2 mm2. The embedded resistors can be laser trimmed to a tolerance of <5% for applications that require tighter tolerance. The electrical properties of embedded capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide frequency and temperature range. A few test vehicles were assembled to do system level analysis. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch. In addition, new technologies for embedding a variety of active chips are being developed. A variety of active chips, including a chip having dimensions of one millimeter square, have been embedded and electrically connected to develop high performance packages.