No abstract

Asynchronous circuits offer promise in handling current and future technology scaling challenges. Unfortunately, their impact has been limited by the lack of design automation. We present A-NTUPLACE, a timing-driven placer uniquely suited to handling quasi delay-insensitive circuits. Our tool uses a generalization of repetitive event rule systems to identify critical signal transitions. The cell placement engine, based on a leading academic placer, NTUPlace3, incorporates net weights to minimize critical wirelengths as well as a novel balancing scheme to ensure isochronic fork constraints are met. We show that our placer is effective at both prioritizing selected nets and balancing forks, demonstrating improvements in 3 of our 4 benchmarks.

Self-timed chip designs are commonly specified in a high-level message-passing language called CHP. This language is closely related to Hoare's CSP except it admits erroneous behavior due to the necessary limitations of efficient hardware implementations. For example, two processes sending on the same channel at the same time causes glitches and short circuits in the physical chip implementation. If a CHP program maintains certain invariants, such as only one process is sending on any given channel at a time, it can guarantee an error-free execution that behaves much like a CSP program would. In this paper, we present an inferable effect system for ensuring that these invariants hold, drawing from model-checking methodologies while exploiting language-usage patterns and domain-specific specializations to achieve efficiency. This analysis is sound, and is even complete for the common subset of CHP programs without data-sensitive synchronization. We have implemented the analysis and demonstrated that it scales to validate even microprocessors.

Abstract-Quasi Delay-Insensitive (QDI) circuits can be created through the procedure of Martin Synthesis, a series of transformations that begin with an executable specification and end in a transistor network. If these transformations are properly applied the circuits will be correct by construction; however if they are improperly applied, finding design errors can be quite difficult. We show that the forward transformations of Martin Synthesis are reversible, and that the inversion of these steps recreates the specification when applied to correctly synthesized circuits. We have created a tool to apply these inversions, and show that it can also be used to verify other compilation methods for QDI circuits. This procedure presents an alternative approach to typical VLSI verification by requiring little designer effort and by reconstructing specifications through transformations.

To any trace preserving action σ : G A of a countable discrete group on a finite von Neumann algebra A and any orthogonal representation π : G → O(ℓ 2 R (G)), we associate the generalized q-gaussian von Neumann algebra A ⋊σ Γ π q (G, K), where K is an infinite dimensional separable Hilbert space. Specializing to the cases of π being trivial or given by conjugation, we then prove that ifare ICC, and G, G ′ belong to a fairly large class of groups (including all non-amenable groups having the Haagerup property), thenare the countable, p.m.p. equivalence relations implemented by the actions of G and G ′ on A and B, respectively. Using results of D. Gaboriau and S. Popa we construct continuously many pair-wise non-isomorphic von Neumann algebras of the form L ∞ (X) ⋊ Γq(Fn, K), for suitable free ergodic rigid p.m.p. actions Fn X. * Marius Junge is partially supported by nsf-dms 1201886.