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In this work dynamic module selection is integrated in a scheduling and placement flow of tasks for a Dynamic Network-on-Chip. Several implementations (modules) of a task are considered, which differ in size and execution time. In contrast, most state-of-the-art flows consider one module per task, therefore having a static module selection during compile time. Tasks arrive and need to be scheduled and placed by finding a feasible start time and place, such that they meet their deadlines and area requirements. Tasks that do not meet these requirements are rejected. Heuristics for module selection are presented and integrated in an O(n log n) scheduling and placement flow using EDF-Next-Fit. Evaluation of the dynamic module selection heuristics is performed using synthetic benchmarks. The results show a lower rejection rate of tasks when compared to static module selection.

Summary The ongoing many‐core design aims at core counts where cache coherence becomes a serious challenge. Therefore, this paper discusses how one‐sided communication and the required process synchronization can be realized on a non‐cache‐coherent many‐core CPU. The Intel Single‐chip Cloud Computer serves as an exemplary hardware architecture. The presented approach is based on software‐managed cache coherence for MPI one‐sided communication. The prototype implementation delivers a PUT performance of up to 5 times faster than the default message‐based approach and reveals a reduction of the communication costs for the NAS Parallel Benchmarks 3‐D fast Fourier Transform by a factor of 5. Further, the paper derives conclusions for future non‐cache‐coherent architectures.

The ongoing many-core design aims at core counts where cache coherence becomes a serious challenge. Therefore, this paper discusses how one-sided communication can be implemented on a non-cache coherent many-core CPU. The Intel SCC serves as an exemplary hardware architecture. The presented approach is based on software-managed cache coherence for MPI one-sided communication. The prototype implementation delivers a PUT performance of up to five times faster than the default message-based approach and reveals a reduction of the communication costs for the NPB 3D FFT by a factor of five. Further, the paper identifies drawbacks of the SCC's architecture and derives conclusions for future architectures.

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