Heterogeneous multicores offer flexibility in the form of different core types and Dynamic Voltage and Frequency Scaling (DVFS), defining a vast configuration space. The optimal configuration choice is not always straightforward, even for single applications, and becomes a very difficult problem for dynamically changing scenarios of concurrent applications with unpredictable spawn and termination times and individual performance requirements. This article proposes an integrated approach for runtime decision making for energy efficiency on such systems. The approach consists of a model that predicts performance and power for any possible decision and low-complexity heuristics that use this model to evaluate a subset of possible decisions to choose the best. The model predicts performance by projecting standalone application profiling data to the current status of the system and power by using a set of platform-specific parameters that are determined only once for a given system and are independent of the application mix. Our approach is evaluated with a plethora of dynamic, multi-application scenarios. When considering best effort performance to be adequate, our runtime achieves on average 3% higher energy efficiency compared to the powersave governor and 2× better compared to the other linux governors. Moreover, when also considering individual applications' performance requirements, our runtime is able to satisfy them, giving away 18% of the system's energy efficiency compared to the powersave, which, however, misses the performance targets by 23%; at the same time, our runtime maintains an efficiency advantage of about 55% compared to the other governors, which also satisfy the performance constraints. 63:2 S. Tzilis et al. INTRODUCTIONMulticore architectures often offer heterogeneity and Dynamic Voltage and Frequency Scaling (DVFS). This flexibility provides knobs for trading performance for energy and vice versa thereby improving system efficiency. Commercial examples of such, single-ISA, architectures include the Samsung Exynos [21] and Qualcomm Snapdragon [19] processors. They employ multiple types of cores (power-efficient and high performance), and multiple voltage-frequency pairs per cluster of cores. In this manner, they can potentially adapt to the fluctuating system workload and its needs at runtime. Such runtime variations stem from the number, type, and performance requirements of the workloads running at any given time on the system. Adapting the system to these dynamic changes can balance smooth application operation and performance with energy efficiency.In this context, choosing the optimal system configuration is often not straightforward. Executing an application on a power-efficient core might prolong execution enough to reduce energy efficiency, while choosing a high-performance core poses the opposite risk-an increase of power consumption outweighing performance gains. DVFS adds more complexity to this problem, as it is unclear how a high-performance core at a low frequency and a power-effi...
a b s t r a c tThe DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect-/fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints.
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