This article presents a comprehensive survey of the literature on self-interference (SI) in long-term evolution advanced (LTE-A) and fifth-generation (5G) new radio transceivers and should serve the reader as a guide and starting point for further work on SI management. Current trends in cellular transceiver designs are discussed, and reasons why new technologies, such as carrier aggregation, cause potential sensitivity degradation due to self-interfering signals are highlighted. The survey provides an overview of the most common interference mechanisms and continues with a taxonomy on SI mitigation architectures by comparing the strengths and weaknesses of various techniques.
In RF transceivers operating in carrier-aggregation, spurs are generated on the transceiver chip which may downconvert any blocker signal located at the spur frequency into the receiver baseband. The blocker signal could either be the transceiver's own transmit signal when operating in frequencydivision duplex, or a WiFi-related signal received by the antenna. This so-called modulated spur interference contains the phasenoise (PN) of the involved local oscillator harmonics which created the spur and leads to a degradation of the wanted RX signal. The presented mixed-signal circuit mimics the spur building law including the PN of the harmonics and is, therefore, able to provide a replica of the spur interference including PN modulated components. This replica is then used as a reference signal for the digital cancellation of the main and image modulated spur interference using a widely-linear (WL) cancellation structure. The proposed circuit technique is implemented in 28 nm LP CMOS technology, and measurement results show that the mixed-signal solution outperforms a digital-only WL cancellation with respect to PN cancellation even with high blocker power levels of −15 dBm at the input of the low-noise amplifier.
Direct-conversion transceivers are the predominating architecture in current mobile communication systems. Despite many advantages, this topology suffers from unavoidable mismatches in the analog part, which causes imbalance between the in-phase and quadrature (I/Q) component. In this paper, we present a novel fully digital, blind I/Q imbalance compensation algorithm that features extremely low computational complexity and high compensation performance for a wide range of input signal types. Different to many state-of-the-art compensation schemes, the approach is not based on a gradient descent optimization and does not require any global feedback. This simplifies the implementation at high data rates and reduces the configuration effort to a minimum. For comparison, we examine an existing method of moment-based estimator with similar properties, for which we also provide the detailed insights beyond available literature. For both algorithms, we provide a rigorous mathematical analysis, which is supported by simulations with a focus on various long-term evolution (LTE) signal types. In addition, hardware architectures, including field-programmable gate array (FPGA) verification, are presented for both algorithms.
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